PURPOSE:To obtain an error position decision circuit capable of 3-symbol correction by using a shift register and a ROM so as to obtain each term of an error location polynomial while substituting a power to variables of the said polynomial in the ascending/descending order and obtaining the error location from the combined value. CONSTITUTION:Shift registers 1-4 are preset as shown in figure and shifted by a clock. The register 1 outputs '1' by the first clock, outputs alpha by the next clock and then alpha ... by the suceeding clocks. It is equivalent to obtain (alpha ) , (alpha ) , (alpha ) ... and equivalent to substitute alpha , alpha , alpha ... to the term X of the error location polynomial. As to the register 2, it is equivalent to sigma1(alpha ) , sigma1(sigma ) , sigma1(sigma ) ... and equivalent to the substitution to the term of sigma1X . This is applied similarly as to the registers 3, 4, and the combination of each output is equivalent to the substitution of symbols in the ascending order from alpha to the variable of the error location polynomial (X). Thus, zero output and the measurement of the clock number to be 0 decide what order number of symbol in the code block has an error.

Error location deciding circuit of reed solomon coding and decoding system

Non-timbering construction method of slab with two-directionreinforcing ribs

PURPOSE:To form a decoder of BCH code with only a logic circuit element by finding syndromes at two syndrome generation circuits, respectively, and obtaining an error correction signal by performing the arithmetic processing of those syndromes on a finite field CONSTITUTION:A code system encoded with the BCH code capable of performing error correction for bits less than two is set as input, and first and second syndromes S1, S3 are found from the above code system at the two syndrome generation circuits 1, 2 based on first and second inspection matrices of BCH code Then, a first inspection code P1 is found by performing power multiplication on the syndrome in which a constant is subtracted from the syndrome S1 on the finite field Also, a second inspection code P3 is found by subtracting the constant from the syndrome S3 on the finite field When the code P1 coincides with the code P3 and at least one bit of bit strings of the syndrome S1 is not zero, error correction information can be obtained, and the above code system is inverted according to the error correction information Thereby, it is possible to obtain a decoding system in which an error included in the code system is corrected

Method and device for decoding bch code

PURPOSE:To eliminate the need for a ROM or a PLA from a decoder by using an error location polynomial of S1x +S 1+S 1+S3 so as to eliminate the need for the operation of the term S /S1. CONSTITUTION:A reception series is fed to S1, S3 calculation circuits 2, 3 to generate syndromes S1, S3. the syndromes S2, S3 are fed to S 1, S 3 calculation circuits 5, 6 and an operation circuit 7, from which coefficients of the error location polynomial sigma(x)=S1x +S 1x+S 1+S are detected. The coefficients are fed to a chain search circuit 8. The syndromes S1, S3 are selected from the reception series by switch circuits 11, 14 and inputted to an adder circuit 15 via an operation circuit 9 multiplying alpha , alpha to operate the sigma(x). When the output of the circuit 15 is zero, it is detected by a zero detection circuit 16 to generate a correction signal, which is ANDed by an output of a latch 4A, and the result inverts bits of the reception series from a shift register 19. the corrected data series is outputted from an output terminal 20.

Decoder for bhc code

PURPOSE:To realize the high speed of an error correcting processing by calculating the syndromes of plural codes simultaneously by plural syndrome calculating parts and simultaneously executing the access of the data to a data memory. CONSTITUTION:Input data are written to a data memory 112 at the data block unit of 8 bits. The writing of the input data to the data memory 112 and the calculation of the syndromes of C1 and C2 are simultaneously executed by syndrome calculating parts 101 and 105. The calculated syndrome is successively written into a syndrome memory 110. A correcting action is executed by a series of processings that an error detecting correcting processing part 111 reads the syndrome from a syndrome memory 110, calculates the position and the size of the error and based on the result, and re-writes the erroneous data in the input data on the data memory 112.

Error correcting device

PURPOSE:To simplify the constitution of a device and to decode a coded word in a short time, by obtaining the 1st, 2nd and 3rd syndrome through the use of a shift register from the coded word of 3-error correction BCH and correcting the error with the primitive element of the Galois field of the element. CONSTITUTION:The 1st, 2nd and 3rd syndromes A1, A2 and A3 are outputted from the 1st, 2nd and 3rd syndrome producing circuits 102, 104 and 106 by using a data buffer 101 consisting of shift registers for an input data (a). Further, a correction condition discriminating circuit 108 discriminates if A1 +A2 is zero and a bit number (t) taking S1=A1+alpha as zero is applied to a selection circuit 117. The 1st and 2nd error detection circuits 115 and 116 discriminate if A1 +A2not equal to 0, bit trains S1, S2 and S3 are taken as equation 1, an input bit corresponding to values t1, t2, t3, up to three, of a bit number (t) giving EL(t) is inverted, the others are outputted as they are, and three errors are corrected at an error correction circuit 118.

Decoding system with three-error correction code

PURPOSE:To realize the miniaturization of the titled decoder, by decreasing sufficiently the number of words of an ROM table and using a simple decoder to the double correction BCH code. CONSTITUTION:The 1st syndrome producing circuit 102 produces the 1st syndrome A1 from the received code; and the 2nd syndrome producing circuit 104 produces the 2nd syndrome A2. An error correction inhibiting circuit 113 detects the conditions by which the bit trains of the syndrome A1 are all 0. At the same time, a bit train 1 which shows the original alpha of a Galois master is produced to the subject of each inspection within a code word, and a bit train 2 showing the original[alpha ]of a cube of the train 1 is produced. In addition, the following circuits are provided: a circuit produces a bit train 3 showing the original (S1=A1+alpha of the Galois matter; a circuit that produces a bit train 4 showing the original cube (S3=S1 ) of the Galois matter; and a circuit that produces a bit train 5 showing the original[S2=A2+alpha ]respectively. A comparator 112 compares the originals of the Galois matters between the trains 4 and 5 to perform a correction of error.

Koga Keiichirou

Papers

Decoding system with three-error correction code

Decoder of double error correction code