Kohji Kanba

TL;DR: A scan flip-flop circuit includes first and second master latches, a slave latch, and first, second, and third switches as discussed by the authors, where the first master latch latches a scan input signal and outputs it to the second output terminal in a scan test.

TL;DR: A slave latch circuit has a gate for being supplied with a signal which is an inversion of a signal outputted from a first output terminal and a control signal, generating a signal based on the supplied signals, and outputting the generated signal from a second output terminal.

TL;DR: In this article, a scan flip-flop circuit is constructed by a control circuit for controlling transfer of the usual mode data to the output terminal in synchronization with the second scan clock signal.

TL;DR: In this article, a race-free shift register device with a plurality of series-connected flip-flop circuits and latch circuits is considered, where the bit data to be input to a preceding flipflop circuit is prevented from being prematurely provided to a succeeding flip flop circuit, thereby ensuring prevention of a race condition.