A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Phase shifting circuit manufacture method and apparatus

Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.

Phase shift masking for complex patterns with proximity adjustments

First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI

Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table. The bias table can include both rule-based and model-based actions, and can also include single-edge shapes for completeness. The scanning of the IC layout can be performed in order of increasing or decreasing complexity, or can be specified by the user. The appropriate layout processing actions are applied to matching portions of the IC layout to form the corrected photomask layout. This process can be sequential or batch mode. Shape and action conflicts can be resolved by marking identified/modified elements or by designing rules for orderly resolution of any inconsistencies or overlaps.

General purpose shape-based layout processing scheme for IC layout modifications

Phase information is incorporated into a cell-based design methodology Standard cells have four edges: top, bottom, left, and right The top and bottom edges have fixed phase shifters placed, eg 0 A given cell C will have a phase set created with two versions: 0-180 (left-right) as well as 180-0 Alternatively, the same phase set: 0—0 and 180—180 could be created for a cell The phase sets are selected based on the ability to phase shift the features within the cell C By creating a phase set for most of the cells of a cell library, standard cell placement and routing techniques can be used and phase can then be quickly assigned using a simple ripple technique This ensures a phase compliant design upfront for the standard cell areas In some instances, phase sets are created for every cell in a library

Standard cell design incorporating phase information

A reticle has a phase-shifting pattern region, a normal pattern (chrome pattern) region, and a shielding region. The phase-shifting pattern region has first and second apertures and mask portions located therebetween. The first apertures transmit light opposite in phase to light transmitted by the second apertures. The normal pattern region has apertures and mask portions. The semiconductor chip regions of a resist film formed on a wafer are exposed stepwise through the phase-shifting pattern region. Subsequently, the portions of the semiconductor chip regions exposed through the phase-shifting pattern region are exposed through the normal pattern region.

Reticle and pattern formation method

PROBLEM TO BE SOLVED: To suppress the error in dimensional accuracy based on a difference between pattern intervals in pattern formation using a phase shift mask. SOLUTION: At the time of forming rest patterns by using the phase shift mask 4 varying in the phases of the transmissive regions on both sides of light shielding regions by 180°, the widths of the light shielding regions 5A and light shielding regions 5B of the mask 4 are changed according to the intervals with the adjacent patterns at the time of the exposure of the positive resist 1, by which the fine patterns of the same line width are formed with the good dimensional accuracy. COPYRIGHT: (C)1998,JPO

Photomask and pattern formation

PURPOSE: To make it possible to form a mask corrected in data by evaluating the processing shapes in a lithography stage and extracting the parts which do not satisfy regulated margins. CONSTITUTION: The mask data designed by a prescribed designing device is inputted in a master data input section 102. Next, the inspection region from the mask data is extracted in an inspection region extracting section 103. The light intensity distribution in the inspection region is then calculated in a light intensity calculating section 104. The development dissolving rate distribution of a resist is calculated in a development dissolving rate calculating section 106. The light intensity distribution and the development dissolving rate distribution are coupled by coupling the light intensity distribution and the development dissolving rate distribution in a shape calculating section 105, by which the processing shapes in the lithography stage are calculated. Next, the margins in the lithography stage of the processing shapes are inspected in an inspection section 107. The parts where the margins satisfy the requirements are extracted in an alarming point extracting section 108. These parts are displayed as warning points on a CRT, etc., in a display section 109.

Mask data verifier, mask data former mask data verifying method, mask data forming method and auxiliary pattern forming method

PROBLEM TO BE SOLVED: To prevent the deterioration in depth of focus(DOF) as some of the layouts of fine hole patterns make the arrangement of auxiliary patterns infeasible in forming the fine hole patterns by using a photoresist and a mask arranged with the auxiliary patterns SOLUTION: The fine hole patterns are formed by using the mask arranged with the negative resist and the auxiliary patterns The fine hole patterns which are high in the depth of focus(DOF) of both of the isolated and dense patterns are formed COPYRIGHT: (C)2003,JPO

Phase shift mask and hole pattern forming method using the same

PROBLEM TO BE SOLVED: To decease the width dimensions of line parts without entailing the enlargement of the dimensions of space parts. SOLUTION: A first photomask 11 drawn only with a first circuit pattern A of a line width of a prescribed value or below among the plural circuit patterns having electrodes and wiring and a second photomask 12 drawn only with the second circuit pattern B having the line width larger than the prescribed value among the plural circuit patterns are formed. A conductive film is subjected to etching by using a first mask pattern formed by using the first photomask 11 and a second mask pattern formed by using the second photomask 12 as a mask, by which the electrodes and wiring consisting of the conductive film are formed. COPYRIGHT: (C)2002,JPO

Koji Matsuoka

Papers

Reticle and pattern formation method

Photomask and pattern formation

Mask data verifier, mask data former mask data verifying method, mask data forming method and auxiliary pattern forming method

Phase shift mask and hole pattern forming method using the same

Photomask device and pattern forming method