In wireless environments, transmission and reception costs dominate system power consumption, motivating research effort on new technologies capable of reducing the footprint of the radio, paving the way for the Internet of Things. The most important challenge is to reduce power consumption when receivers are idle, the so called idle-listening cost. One approach proposes switching off the main receiver, then introduces new wake-up circuitry capable of detecting an incoming transmission, optionally discriminating the packet destination using addressing, then switching on the main radio only when required. This wake-up receiver technology represents the ultimate frontier in low power radio communication. In this paper, we present a comprehensive literature review of the research progress in wake-up radio (WuR) hardware and relevant networking software. First, we present an overview of the WuR system architecture, including challenges to hardware design and a comparison of solutions presented throughout the last decade. Next, we present various medium access control and routing protocols as well as diverse ways to exploit WuRs, both as an extension of pre-existing systems and as a new concept to manage low-power networking.

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Ultra Low Power Wake-Up Radios: A Hardware and Networking Survey

In this work, we implemented and evaluated a fully integrated 2.4 GHz CMOS RF transceiver using various low-power techniques for low-rate wireless personal area network (IEEE 802.15.4 LR_WPAN) applications in 0.18-μm CMOS technology. In order to achieve an ultra low power consumption, a RC oscillator (OSC) operating below 200 nA, a regulator operating below 200 nA for sleep mode, a quick start block for the crystal oscillator, a passive wake-up circuit, a LNA with negative gm, a current bleeding mixer, and a stacked VCO are all implemented in this transceiver. The transmitter achieves less than 5.0% error vector magnitude (EVM) at 5 dBm output, and the receiver sensitivity is -101 dBm. The sensitivity of the wake-up block is -29.8 dBm. The current consumption is below 14.3 mA for the data receiving mode, 16.7 mA for the transmitter, and less than 600 nA for the sleep mode from a 1.8 V power supply. That is considered to be lowest for the 2.4 GHz CMOS ZigBee transceiver compared to open literature results.

An Ultra Low-Power CMOS Transceiver Using Various Low-Power Techniques for LR-WPAN Applications

Two integrated, highly efficient RF-to-dc rectifier circuits are presented. The rectifier circuits are based on improved Dickson charge pump models and are fabricated using 65-nm CMOS GlobalFoundries process. The designs utilize diode-connected metal–oxide–semiconductor field-effect transistors instead of the conventional Schottky diodes to provide a fully integrated circuits. A detailed analytical model that supports the improved circuit model is given. The measurement results of both rectifier circuits show good agreement with the simulation results. The fabricated rectifiers’ start to operate at −17.5-dBm input power. The tested frequency of operation of the rectifier circuits is 953 MHz (GSM900 band), however, other frequency bands such as 2.4 GHz (Bluetooth/WLAN) could be covered with proper impedance matching. The measured peak power conversion efficiency (PCE) of the implemented rectifiers are 84.37% and 56.16% at input power levels of −12.5 and −15 dBm, respectively. To the best of our knowledge, this is the highest achieved PCE for the class of rectifiers at such low input power level in the literature. High sensitivity and excellent PCE of the presented rectifiers are ideal for utilization in wireless sensor network, Internet of Things, energy harvesting, and biomedical applications.

High Efficiency Energy Harvesters in 65nm CMOS Process for Autonomous IoT Sensor Applications

The voltage multiplier (VM) circuit is a cascade arrangement designed from a series of rectifiers to obtain high DC output voltage. In this classical approach, the DC voltage which is getting generated in the present stage contributes to the next stage. This phenomenon is recurring at every stage resulting into higher DC output voltage than previous. The proposed signaling scheme enables the use of the rectified DC voltage/stage in a classical way along with the involvement of instantaneous input RF voltage. As a result, higher output DC voltage and improved power conversion efficiency (PCE) will be achieved as compared to a conventional VM circuit signaling scheme. The conventional VM circuit used in this work was designed by stacked series arrangement of three standard differential drive rectifiers. Similarly, the proposed VM circuit was formed by implementing proposed signaling scheme into the conventional VM circuit. These architectures were implemented in a standard 0.18 $$\upmu$$μm CMOS technology The measurements were done by using input RF signal frequency of 433 MHz for resistive load values of 30, 100 K$$\Omega$$Ω, and 1 M$$\Omega$$Ω respectively. The measured results show that the proposed VM scheme has 22---32 % better power conversion efficiency than the conventional VM scheme.

A novel cascading scheme to improve the performance of voltage multiplier circuits

The fully integrated complementary metal-oxide-semiconductor (CMOS) transmitter (Tx), an essential component in every wireless communication system, ensures highly efficient signal processing and data transmission. The performance of the Tx significantly affects the overall performance of the wireless device [1]. The demand for low-power, low-cost wireless devices operating at the 2.4-GHz band has led to extensive research on RF architecture and circuit design. A well-defined architecture, including linear and simple functional block synthesis, is crucial to the design of the RF Tx for various applications [2]. The state-of-the-art CMOS Txs proposed in the literature to improve Tx performance analyses are vital to understanding application-oriented RF Tx design techniques for further research.

CMOS Transmitters for 2.4-GHz RF Devices: Design Architectures of the 2.4-GHz CMOS Transmitter for RF Devices

A 2.4 GHz band high-efficiency RF rectifier and high sensitive dc voltage sensing circuit is implemented. A passive RF to DC rectifier of multiplier voltage type has no current consumption. This rectifier is using native threshold voltage diode-connected NMOS transistors to avoid the power loss due to the threshold voltage. It consumes only 900nA with 1.5V supply voltage adopting ultra low power DC sensing circuit using subthreshold current reference. These block incorporates a digital demodulation logic blocks. It can recognize OOK digital information and existence of RF input signal above sensitivity level or not. A low power RF rectifier and DC sensing circuit was fabricated in 0.18um CMOS technology with native threshold voltage NMOS; This RF wake up receiver has -28dBm sensitivity at 2.4 GHz band.

High sensitive RF-DC rectifier and ultra low power DC sensing circuit for waking up wireless system

This single-chip RF and modem transceiver provides a complete radio interface between the radio block, digital demodulation including time and frequency synchronization and data buffering. The number of external components is minimized so that only one crystal and one resistor and several decoupling capacitors are required. The bidirectional differential antenna pins are commonly used for RX and TX, therefore, no external antenna switch is needed. One on chip low-drop voltage regulator provides the analog and digital 1.8 V supply. The RX and TX signal processing part is implemented using 0.18 mum libraries, utilizing the low power consumption and the high density of the technology. The transceiver is implemented in a 1P6M 0.18 mum CMOS Technology with MIM capacitors. The receiver sensitivity is -94.7dBm for 1% packet error rate defined in IEEE 802.15.4 standard and error vector magnitude (EVM) of transmitter is 10% for 2.4 GHz band.

A fully integrated 2.4 GHz IEEE 802.15.4 transceiver for Zigbee applications

We analyze the capacity of an ad hoc networks when cognitive radio (CR) is deployed for traffic load reduction. This capacity, the per-link capacity, is defined as an average of Shannon capacities achieved by all links in a route. For this purpose, we propose a generalized ad hoc network model which is based on CR in its retransmission. Given the model, our analysis shows that the capacity is Ω(1/N log N)1 according to the number of nodes N, outperforming the conventional ad hoc network of which the capacity is Ω(1/N2. Further, we can also see that there exists an optimal signal-to-interference ratio (SIR) threshold that maximizes the capacity by controlling the average number of nodes served depending on CR in a link.

Koon-Shik Cho

Papers

High sensitive RF-DC rectifier and ultra low power DC sensing circuit for waking up wireless system

A fully integrated 2.4 GHz IEEE 802.15.4 transceiver for Zigbee applications

The capacity of cognitive ad hoc networks