A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A DNA sequencing system and method are described to detect the presence of radiant energy emitted from different excited reporter dye-labeled species (DNA fragments) following separation in time and/or space, and the identity of the species which emit radiant energy closely spaced in wavelength. Functions of the emitted energy are obtained which vary over the wavelengths of the closely spaced spectra in different senses and the functions ratioed, whereby the ratio is indicative of the identity of the DNA fragments. The emitting portion of the reporter-labeled DNA fragment is preferably one of a family of fluorescent dyes based on 9-carboxyethyl-6-hydroxy-3-oxo-3H-xanthene. These xanthene dyes are covalently attached to the DNA fragments through the carboxylic acid functionality, preferably via an amide linkage. The dyes may be protected by including an alkoxy group at the 9-position. A spacer may be inserted between the dye and the amine. The fluorescent dye preferably is attached to the DNA chain terminators and provides many advantages. Thus only DNA sequencing fragments resulting from bona fide termination events will carry a reporter. The DNA sequencing may also be labeled using the xanthene dyes which have general utility as fluorescent labels. Also acyclonucleoside triphosphates are described as being useful as chain terminators in DNA sequencing using a modification of the Sanger method.

Method, system and reagents for DNA sequencing

A semiconductor device comprising a capacitor of a laminated structure and a method of manufacturing thereof, in which first conductive layer and second conductive layer of different materials or different compositions are stacked alternately with dielectric films interposed therebetween and the first conductive layers and the second conductive layers are interconnected respectively at a time by suitably combining a selective etching method and an anisotropic etching method.

Method of making multilayer capacitor memory device

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

Mixed analog and digital integrated circuits

PURPOSE:To establish the input level at an effective level with ease in a CMOS structure without reducing operating speeds by a method wherein the threshold voltage is different between the input circuit and inner circuit. CONSTITUTION:A chip 10, in a semiconductor integrated circuit of a complementary MOS transistor type, has an internal circuit 11 located at the middle and inout circuits 21-24 surrounding the inner circuit 11. The Vthp of PMOSTs constituting the inner circuits 21-24 is a Vthp2 good enough for the input level to realize a TTL level while the Vthp of PMOSTs constituting the inner circuit 11 is a Vthp1 not causing a reduction in the operating speeds. Accordingly, the input circuit 21-24 are well aligned well to meet an input of the TLL level, and the operating speeds inside the inner circuit 11 are not reduced.

Semiconductor integrated circuit

PURPOSE:To set the input levels of an IC to various values by composing the IC of a plurality of the first conductive type first MOS transistor group and the second conductive type second MOS transistor group, selecting at least one transistor from the groups, providing an arbitrary channel length, and using it for an inverter of an input circuit CONSTITUTION:P-channel MOS transistor regions 3-1-3-3 and N-channel MOS transistor regions 4-1-4-3 are formed among an input terminal 1, an output terminal 2, a power terminal 6 and a ground terminal 7 At this time, the ratio of the channel length of the transistors of the respective channels is set to the desired value A source region of the P-channel element is connected to the terminal 6, the source region of the N-channel element is connected to the terminal 7, and the terminal 2 is connected to a drain region, and connected to the gate electrodes of the terminal 1 In this manner, the contacting holes and the length of the metal wiring region are selected to obtain various input levels

Semiconductor integrated circuit device

PURPOSE:To enable the input level to be set to different values by a method wherein, when manufacturing the input circuit of an LSI by a master slice system, a plurality of MOS transistor sets with P channel type and N channel type are formed, and each transistor is made different in the channel width at 1:2:4. CONSTITUTION:With an output terminal 2 constituted of a metallic wiring band placed between, a power source terminal 6 and an earth terminal 7 using the same metallic wiring band are provided on the both sides thereof, and, between terminals 2 and 6, a plurality of P channel type MOS transistor regions 3-1-3-3 are formed. Between terminals 7 and 2, N channel type MOS transistors 4-1-4-3 are provided, and these are connected to the terminal 2 by metallic wiring regions 8-1-8-6 for connection. On the other hand, to the input terminal 1, a polycrystalline gate wiring is connected and connected to contact holes 5-1-5-6 of each transistor. In such a constitution, the channel width ratio of transistors is set 1:2:4, then a necessary transistor is selected, and accordingly different input levels are obtained.

Semiconductor ic device

PURPOSE:To obtain a active filter which is capable of switching the central frequancy and the band width by controlling the switch element electornically and which is suitably manufactured for an integrated circuit Thus, the active filter can be applied effectively for a selective calling unit of a mobile radio apparatus

Programable active filter

PURPOSE:To obtain a noise-free circuit which can control the duty of an output to 50% or controls outputs independently by providing an oscillator with 1st and 2nd constant current sources, a control circuit controlling the 1st and 2nd current sources and a means intermittently connecting and cutting the 1st and 2nd current sources CONSTITUTION:A P channel MOS transistor (hereinafter referred to PchTR) 23 is a current mirror for a current source PchTR 22 An NchTR 34 is a current mirror for NchTRs 32 and 33 and its current value is decided by a current source 40 The titled oscillator is constituted by providing a circuit consisting PchTRs 21 and 22 and NchTRs 31 and 32 with an inverter 13 As for the action, the PchTR 21 is turned on with the output of an inverter 11 at a low level, and a capacitor 50 is charged With the output of the inverter 11 at a high level, the NchTR 31 is turned on to discharge the capacitor 50, and a target triangle wave can be obtained Thus an inverter 12 can obtain an output waveform with a duty of 50%

Koyada Hiroshi

Papers

Semiconductor integrated circuit

Semiconductor integrated circuit device

Semiconductor ic device

Programable active filter

Current control oscillator