A circuit for providing a control voltage to a switch includes a capacitor, a first pair of switches for coupling the capacitor to an input voltage source and a second pair of switches for coupling the capacitor to the switch. The first pair of switches is controlled by a control signal in response to the voltage across the capacitor in order to prevent overcharging the capacitor beyond a first predetermined level. The second pair of switches is controlled by a second control signal in response to the voltage across the switch in order to replenish the capacitor voltage when the capacitor voltage falls to a second predetermined level. The first and second pairs of switches are closed during non-overlapping time intervals in order to isolate the switch from the input voltage source, thereby preventing switching transients from affecting the input voltage source and permitting the circuit to be used to drive a variety of switch types arranged in a variety of configurations.

Circuit providing a control voltage to a switch and including a capacitor

Circuits (Fig. 1) that operate with power supplies (VDD) of less than 1 Volt are present. More particularly, circuits (Fig. 1) that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (M1A, M1B) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor (MOS) to bipolar junction transistors may implement the techniques presented herein.

Low voltage operational transconductance amplifier circuits

A data processing circuit includes a digital data source having an output carrying a sequence of digital signals. A pre-filter is coupled to the output of the digital data source. The pre-filter has a first output that carries a second sequence of digital signals and a second output that carries a third sequence of digital signals. The second sequence of digital signals is time shifted relative to the third sequence of digital signals. The circuit also includes an interpolation circuit with a first input coupled to the first output of the pre-filter and a second input coupled to the second output of the pre-filter.

Efficient interpolator for high speed timing recovery

A filter for filtering micro-emboli from a patient's blood during an angioplasty procedure is disclosed which comprises a plurality of curved wires connected to a rod between a first connector fixed with respect to the rod and a second connector slidingly mounted on the rod. Two layers of filter material are connected to opposite sides of the wires, and each layer includes perforations which are offset from the perforations in the other layer. When the rod and the wires are disposed within a catheter, the inner wall of the catheter compresses the wires toward the rod and when the rod is extended from the catheter, the wires resume their curved shape and pull the sliding connector along the rod toward the fixed connector.

Apparatus for trapping emboli

A receiver includes a common-gate low noise amplifier (LNA) configured to receive an RF input signal and produce an amplified RF signal A down-converting passive mixer is configured to mix the amplified received RF input signal with a local oscillator signal generated by a local oscillator to generate a down-converted amplified signal An amplifier is configured to amplify the down-converted signal and has an input impedances in on the order of ohms Only a single LNA may be required to receive RF inputs in all frequency bands of a multi-band communication standard

Radio frequency receiver architecture

A low voltage, broadband differential operational amplifier which eliminates the long tail current source from the amplifier, thereby relieving the headroom requirements by a few tenths of a volt. An input common mode feedback circuit is used to overcome the problems arising from the removal of the long tail current source of prior art circuits. This circuit monitors the common mode feedback current and when the value of the current exceeds a specified range around the nominal amplifier bias current, an appropriate correction in the common mode input voltage is made. This novel amplifier will be valuable for use in pipelined analog-to-digital converter applications, as well as many other low voltage and/or portable applications.

Low-voltage, broadband operational amplifier

A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next oscillator clock edge rather than a feedback clock edge. This technique can be used to significantly reduce digital phase lock loop circuit power by disabling feedback divider and sync FF once initial frequency lock is established, provided phase jitter of digital phase lock loop circuit is low enough so that there is no cycle slip. This technique can also be used to multiply the effective reference clock frequency of digital phase lock loop circuits to increases the loop bandwidth, thus reducing the phase noise. Both the applications of this technique can be combined in some circuits.

Low power digital phase lock loop circuit

A MOS track-and-hold circuit incorporating cancellation of error due to switch feedthrough is described. To eliminate the channel charge feedthrough due to oxide capacitance, a switched capacitor source (22) is connected to be charged to a voltage V1 during the "hold" phase and between the input node (12) and the switch gate (17) to provide a voltage V1-Vin during the "track" phase. A dummy transistor (26) biased in an "off" condition has its drain connected to the holding capacitor (15) and its gate switched between ground and the output terminal (Vout which tracks Vin) to also cancel the feedthrough from the gate-drain overlap capacitance and any gate-drain parasitic capacitance.

MOS sample and hold circuit

Apparatus and method for operation of a phase locked loop for a wireless receiver are disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of the first plurality of cycles in response to the step of comparing.

Loop bandwidth enhancement technique for a digital pll and a hf divider that enables this technique

A novel Finite Impulse Response ("FIR") filter (10)" is provided with precise timing acquisition. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (34). A plurality of slave sample and hold circuits (36-44) are coupled to the output of the master sample and hold circuit. The outputs of the slave sample and hold circuits (36-44) are multiplexed to a plurality of multipliers (14-22) in a round robin manner.

Krishnasawamy Nagaraj

Papers

Low-voltage, broadband operational amplifier

Low power digital phase lock loop circuit

MOS sample and hold circuit

Loop bandwidth enhancement technique for a digital pll and a hf divider that enables this technique

Fir filter architecture with precise timing acquisition