A system and method for caching network resources in an intermediary server topologically located between a client and a server in a network. The intermediate server preferably caches at both a back-end location and a front-end location. Intermediary server includes a cache and methods for loading content into the cache as according to rules specified by a site owner. Optionally, content can be proactively loaded into the cache to include content not yet requested. In another option, requests can be held at the cache when a prior request for similar content is pending.

System and method for network caching

A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and (2) correcting the data inconsistency states so that the operation may be executed in a correct and consistent manner. In particular, the method is adapted to address two kinds of data inconsistency states: (1) A request for a operation from a system unit to main memory when the location to be written to is present in the cache of some processor unit-in such a case, data in the cache is "stale" and the data inconsistency is avoided by preventing the associated processor from using the "stale" data; and (2) when a read operation is requested of main memory by a system unit and the location to be read may be written or has already been written in the cache of some processor--in this case, the data in main memory is "stale" and the data inconsistency is avoided by insuring that the data returned to the requesting unit is the updated data in the cache. The presence of one of the above-described data inconsistency states is detected in a SCU-based multi-processing system by providing the SCU with means for maintaining a copy of the cache directories for each of the processor caches. The SCU continually compares address data accompanying memory access requests with what is stored in the SCU cache directories in order to determine the presence of predefined conditions indicative of data inconsistencies, and subsequently executes corresponding predefined fix-up sequences.

Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system

A hierarchical searching technique is used to find the first memory location of a calendar queue with a validity bit of “1” (that is, the lowest time stamp). The bit string at any level l (l≠0) can be stored in a RAM of size g l M l−1 . The string at the highest level in the hierarchy (l=0) can be stored in an M 0 bit register. The number of address bits need to address any bit at a level l may be expressed as: m l = log 2  M l = m l - 1 + log 2  g l = ∑ i = 0 l  log 2  g i ,  where   g 0 = M 0 . ( 11 ) Equation (11) illustrates a method of the present invention for addressing in a hierarchical search. That is, m 0 most significant bits of the time stamp address should be used at level 0 . Then, at level l, the complete address used at upper level (l−1) will be used to locate the proper g l bit word in its g l M l−1 memory. Another log 2 g l bits following the previous m l−1 bits is extracted from the time stamp address and used to locate the proper bit in the g l bit word that has just been identified. In this way, the search time depends on the number L of levels. Thus, a scheduler based on the present invention can schedule large numbers of flows to be placed on a high speed data link (i.e., with a small time slot). A two (2) dimensional shaper uses a similar hierarchical searching and addressing technique. Finally, any overflow of binary encoded time stamp and system potential values is tracked so that time stamp aging does not cause problems.

Methods and apparatus for fairly scheduling queued packets using a ram-based search engine

An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention disclosed is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles. It is understood that the number of processes who's states are duplicated may easily be a large number n.

Method and apparatus for rapidly switching processes in a computer system

A cache memory (10) for a data processing system having a tag array (22) in which each tag word can contain a sector address (A18-A31) and represents a predetermined set or block group of consecutively addressable data block locations in a data array (26). The lower order set address bits (A8-A17) concurrently access the tag word and its associated group of block locations in the data array while individual blocks within the group are accessed by supplemental block bits (A6-A7). Each tag word read out must compare equal (28) with the high order sector bits (A18-A31) of the address and an accompanying validity bit (Vi) for each accessed block location in its group must be ON in order to effect (30) a hit. Also described are circuits for writing into the cache and adapting the cache to a multi-cache arrangement.

Set associative sector cache

A cache memory organization is shown using a miss information collection and manipulation system to insure the transparency of cache misses. This system makes use of the fact that the cache memory has a faster rate of operation than the rate of operation of central memory. The cache memory consists of a set-associative cache section consisting of tag arrays and control with a cache buffer, a central memory interface block consisting of a memory requester and memory receiver together with miss information holding registers section consisting of a miss comparator and status collection device. The miss information holding register section allows for an almost continual stream of new requests for data to be supplied to the cache memory at the cache hit rate throughput.

Kroft David

Papers

Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses