This invention relates to newly identified polynucleotides and polypeptides in the phytic acid biosynthetic pathway, variants and derivatives of same; methods for making the polynucleotides, polypeptides, variants, derivatives and antagonists. In particular the invention relates to polynucleotides and polypeptides of the inositol 1,3,4-trisphosphate 5/6-kinase gene family. In particular this invention relates to using the newly identified polynucleotides and polypeptides to modulate the phytic acid biosynthesis in such a way as to decrease phytate and/or increase non-phytate phosphorous, especially in corn or soy animal feedstuffs.

Phytate polynucleotides and methods of use

An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load. The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit V SS /V DD . A gate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor. The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the V SS /V DD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.

Electrostatic discharge protection circuit triggered by capacitive-coupling

Semiconductor diodes having a low forward voltage conduction drop, a low reverse leakage current and a high voltage capability suitable for use in integrated circuits as well as for discrete devices. The semiconductor diodes are fabricated as field effect devices having a common gate and drain connection by a process which provides very short channels, shallow drain regions and longitudinally graded junctions. Continuation of the gate/drain contact layer over specially located tapered edge field oxide (34) maximizes the breakdown voltages of the devices. The preferred fabrication technique utilizes four masking steps, all without any critical mask alignment requirements. Various embodiments are disclosed.

Semiconductor diodes having low forward conduction voltage drop and low reverse current leakage

Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Methods of forming field effect transistors and field effect transistor circuitry

A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Low voltage transient voltage suppressor and method of making

An on-board integrated circuit chip signal source which allows operation of the chip from previously incompatible and excessively high amplitude signal sources, and as well powers the chip from such sources as the input signal, a clock, etc. The invention utilizes a 3 plate capacitor, with the bottom plate formed of a heavily doped region of the silicon substrate. Signal is applied between the outside plates of the capacitor and a proportion of the signal is received between the center plate and one of the outside plates. A diode clamp connected between the center plate and a reference potential fixes the derived peak and average signal levels.

Kubinec James C

Papers

Means for coupling incompatible signals to an integrated circuit and for deriving operating supply therefrom

Halbleiterbauteil mit einem dreiplattigen kondensator