In a microelectronic component having conductive vias ( 114 ) passing through a substrate ( 104 ) and protruding above the substrate, conductive features ( 120 E.A, 120 E.B) are provided above the substrate that wrap around the conductive vias' protrusions ( 114 ′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

Making multilayer 3d capacitors using arrays of upstanding rods or ridges

A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

Microelectronic conductive routes and methods of making the same

A TSV structure includes a substrate comprising at least a TSV opening formed therein, a conductive layer disposed in the TSV opening, and a bi-layered liner disposed in between the substrate and the conductive layer. More important, the bi-layered liner includes a first liner and a second liner, and a Young's modulus of the first liner is different from a Young's modulus of the second liner.

Through-silicon via structure

Stacked capacitor structures using TSVs are provided. In one aspect, a stacked capacitor structure includes: a first substrate having at least one first capacitor formed in a TSV in the first substrate; and a second substrate, bonded to the first substrate, having at least one second capacitor formed in a TSV in the second substrate, wherein the first capacitor and the second capacitor each comprises a first electrode and a dielectric that both surround a second electrode that is at a core of the TSV, wherein the dielectric separates the first electrode from the second electrode, and wherein the second substrate is bonded to the first substrate such that the first capacitor is stacked on the second capacitor. A method of forming a stacked capacitor structure is also provided.

Forming a stacked capacitor

The present invention provides a method for fabricating a capacitor structure, including the steps of: providing a substrate; forming a first conductive structure and a dielectric structure over the substrate, wherein the first conductive structure is enclosed by the dielectric structure; forming a first trench in the dielectric structure, so that a first surface of the first conductive structure is exposed through the first trench; forming a first capacitor electrode and a capacitor dielectric layer on a bottom and a sidewall of the first trench and on a top surface of the dielectric structure, so that the first capacitor electrode is electrically contacted with the first surface of the first conductive structure; and removing the first capacitor electrode and the capacitor dielectric layer on the top surface of the dielectric structure; forming a second capacitor electrode on a surface of the capacitor dielectric layer. A capacitor structure is also provided.

Kuei-Sheng Wu

Papers

Capacitor structure and fabricating method thereof