Thread signaling in multi-threaded network processor

An improved mechanism for communicating between computer programs is provided. In a preferred embodiment of the present invention, a computer system has a source computer program, a destination computer program and a communication mechanism for sending a communication from the source computer program to the destination computer program. The communication mechanism contains a concurrency management mechanism for handling events when a communication is pending. The source computer program sends a communication to the destination computer program using the communication mechanism. While the remote communication is pending, the concurrency management mechanism of the preferred embodiment provides concurrency management. The source computer program then receives a reply to the communication from the destination computer program.

Concurrency management component for use by a computer program during the transfer of a message

A computer application program executing on a computer, such as a portable computer, is selected for termination by first identifying computer application programs executing on the computer. A priority value is assigned to each of the identified computer applications. The priority value is based on multiple characteristics of the identified computer application programs. The computer application program with the smallest priority value is automatically terminated. If the computer application program with the smallest priority value is in a modal state in which it waits for a response from a user, then a default response is provided to the application prior to terminating the computer application program. The characteristics associated with the computer application programs may include average launch times, average memory usages, a class or type of application, frequencies of usage, and an amount of data stored on the computer by the computer application program.

System and method for terminating applications

PCT No. PCT/FI93/00304 Sec. 371 Date Apr. 3, 1995 Sec. 102(e) Date Apr. 3, 1995 PCT Filed Jul. 28, 1993 PCT Pub. No. WO94/03855 PCT Pub. Date Feb. 17, 1994A method for managing resources allocated in a computer, wherein the allocated resources are maintained or released by time monitoring. In the method, a task controller is allocated for the management of resources required for a task to be executed. The controller allocates resources required to execute the task. The controller starts time monitoring in each resource. If required by the task, the controller renews the resource allocations before the expiry of the respective time monitoring periods, and the controller releases all resources allocated for the task after the completion of the task.

Method for managing resources allocated in a computer

Resource management architectures implemented in computer systems to manage resources are described. In one embodiment, a general architecture includes a resource manager and multiple resource providers that support one or more resource consumers such as a system component or application. Each provider is associated with a resource and acts as the manager for the resource when interfacing with the resource manager. The resource manager arbitrates access to the resources provided by the resource providers on behalf of the consumers. A policy manager sets various policies that are used by the resource manager to allocate resources. One policy is a priority-based policy that distinguishes among which applications and/or users have priority over others to use the resources. A resource consumer creates an “activity” at the resource manager and builds one or more “configurations” that describe various sets of preferred resources required to perform the activity. Each resource consumer can specify one or more configurations for each activity. If multiple configurations are specified, the resource consumer can rank them according to preference. This allows the resource consumers to be dynamically changed from one configuration to another as operating conditions change.

Methods and architectures for resource management

In a microcomputer system, having independently programmed tasks and a master control processing unit (CPU), tasks can be switched independent of the master CPU through the use of a multi-task support processor which may, for example, be connected to the microcomputer system via an input/output (I/O) port. The multi-task support processor includes a memory for storing task control programs, a data memory and task control memory, a timer, a controller for controlling multi-task operations, and a master CPU interface element. Tasks including task control commands are stored in a memory for execution by the master CPU. The master CPU, upon encountering a task control command, sends that command to the multi-task support processor which becomes activated to control the switching and communications between the tasks under the direction of the received task control command, so that tasking control may be performed independent of the master CPU.

Multi-task execution control system

PURPOSE:To easily detect a hand map by displaying the incompletion of a handshake when a handshake processing time exceeds a set value. CONSTITUTION:A control element 1 is constituted as a processor which codes messages of the standard digital interface 2 and realizes an interface function, and a one-chip microcomputer which incorporates I/O ports for controlling the handshake and a timer for time-out setting is used. A master CPU2 and dedicated bus transceivers 3 and 4 are connected to this control element 1, and the bus of the standard digital interface is connected to those dedicated bus drivers 3 and 4. The timer in the control element 1 is started at the start of a source handshake or acceptor handshake, and the incompletion of the handshake is displayed when the handshake processing time exceeds the set time of the timer.

Standard digital interface device

PURPOSE:To relieve remarkably the load of a CPU side by judging whether or not a memory area is in use to seek the idle area of a size requested by a task, thereby allowing a device other than the CPU to assign data to the task. CONSTITUTION:When a command MALC10 is received from a master CPU, an error in an input data is checked and when not error is detected, a memory map MEMMAP is checked and whether or not a requested work memory is idle is checked and when an idle area is found out, ''1'' is set to the corresponding bit on the memory map MEMMP by a size request by the task outputting the command. A respective value is set to a head address of an occupied memory and size in a task control block TCB and the occupied memory and head address of an occupied memory and size in a task control block TCB and the occupied memory and head address are written in a command parameter register CPIO. A normal end code is set to a command/status registor CNST finally and the routine restors to a main routine.

Multi-task controlling device

PURPOSE:To enable all CPUs to be applied to a microcomputer multitask control system by controlling the execution of a task in accordance with a command generated from a unit other than the CPU. CONSTITUTION:A multitask support proccessor (MTSP) element 1 is connected to the system through a master CPU2 and an internal bus 3 similarly to the other peripheral input element 4. A program memory 5 programs an initializing program of the MTSP element 1 and plural tasks independently and is constituted by connecting a memory 6 as a data memory to be used by respective tasks. The MTSP element 1 is provided with a task scheduling function for attaining the multitask system, synchronizing and communicating functions of tasks, a memory controlling function, a clock function, etc. An access from the CPU2 to the MTSP element 1 is executed by a command and an access from the MTSP element 1 to the CPU2 is executed by interruption.

Controlling method of multitask

PURPOSE:To improve the processing speed of a user program by applying time control of a task with an internal timer output possible for count to allow a master CPU to switch the task during execution thereby attaining time setting and reading from the master CPU. CONSTITUTION:A multi-task control element connected to the master CPU1 is provided with register groups SPN and MIC or the like accessible from the master CPU and with an interruption control circuit INTC as an interface circuit. Moreover, a task control block TCB possible for handling the task priority, a timer TM for time sharing processing or the like, an area SCA storing the time data to be counted and an internal operation control circuit CONT or the like are provided. The time sharing processing is set by a signal of the timer TM, and also the area SCA is operated, and when the it is concident with the task under execution for the priority and after a prescribed time is elapsed, the master CPU applies processing of interruption to the designated task.

Kuki Masaru

Papers

Multi-task execution control system

Standard digital interface device

Multi-task controlling device

Controlling method of multitask

Device for multi-task control