An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.

Architecture and interconnect scheme for programmable logic circuits

An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

Method and apparatus for universal program controlled bus architecture

A Field Programmable Gate Array (FPGA) device includes a plurality of variable grain blocks (VGBs) and a plurality of interconnect lines for providing program-defined routing of signals between the VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. Each CBB includes 6 term inputs, 2 control inputs and one direct connect output. Each CBB includes two configurable building elements having 3 term inputs and 1 control input, respectively. The plurality of interconnect lines includes a direct connect architecture for providing programmably-selectable, dedicated connections between a center VGB, in particular a CBB, and neighboring VGBs. The direct connect architecture and positioning of inputs and outputs enables 1) enhanced flexibility and efficiency in the configuration placement and routing software 2) efficiently emulates random logic nets and 3) reduces many direct connect line wire lengths.

Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits

Field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gate arrays. Hierarchical interconnection structures for field programmable gate arrays are proposed. They help overcome these problems. Logic blocks in a field programmable gate array are grouped into clusters. Clusters are then recursively grouped together. To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed. The field programmable gate arrays with new architecture can be efficiently configured with existing computer aided design algorithms. The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously. Experiments on benchmark circuits show that density and performance are significantly improved.

Hierarchical interconnection structures for field programmable gate arrays

A hierarchical switch matrix in a very high-density programmable logic device (CPLD) interconnects a multiplicity of programmable logic blocks (101) in the CPLD. A new level of functionality coupled with high speed is provided by the hierarchical switch matrix. The hierarchical switch matrix includes three levels, a global switch matrix (165), a segment switch matrix (161) and a block switch matrix (266). The block switch matrix (266) provides a high speed signal path for signals within a programmable logic block (101). The segment switch matrix (161) provides a high speed means of communication for signals within a segment, while the global switch matrix (165) provides a high speed path for communication between segments. The hierarchical switch matrix of this invention provides a fixed, path independent, uniform, predictable and deterministic time delay for each group of signals routed through the hierarchical switch matrix.

A multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices

To overcome the low speed and low density problems in the FPGAs, we must reduce the number of switches used in the routing paths without sacrificing the routability for an FPGA. A hierarchical interconnection architecture for field programmable gate array (FPGA) is described. In every level of the hierarchy, logic blocks or cluster of logic blocks are connected together with switch blocks. Experiments on benchmark circuits are shown. It can be seen that significant improvement on performance is achieved. >

A high performance FPGA with hierarchical interconnection structure

A new interconnection structure for FPGAs is presented The structure is hierarchically divided into two levels Four adjacent logic blocks are grouped together at the first level, and then the group is connected to a bus structure at the second level The functionality of a logic block is enhanced so that less logic blocks are needed and interconnections are simplified Therefore, the performance of the FPGA is much improved >

A hierarchical interconnection structure for field-programmable gate arrays

In this paper we present a new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs to minimize both CLB levels on critical paths and total wire length. We first use a clustering approach to get a level-optimized mapping solution. Then we use a min-cut based block pairing algorithm to minimize the total wire length and the number of used CLBs. Experimental results on the MCNC benchmark circuits show that our algorithm is effective.

Kun-Nen Chen

Papers

A high performance FPGA with hierarchical interconnection structure

A hierarchical interconnection structure for field-programmable gate arrays

A new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs