The emergence of DC fast chargers for electric vehicle batteries (EVBs) has prompted the design of ad-hoc microgrids (MGs), in which the use of a solid-state transformer (SST) instead of a low-frequency service transformer can increase the efficiency and reduce the volume and weight of the MG electrical architecture. Mimicking a conventional gasoline station in terms of service duration and service simultaneity to several customers has led to the notion of ultra-fast chargers, in which the charging time is less than 10 min and the MG power is higher than 350 kW. This survey reviews the state-of-the-art of DC ultra-fast charging stations, SST transformers, and DC ultra-fast charging stations based on SST. Ultra-fast charging definition and its requirements are analyzed, and SST characteristics and applications together with the configuration of power electronic converters in SST-based ultra-fast charging stations are described. A new classification of topologies for DC SST-based ultra-fast charging stations is proposed considering input power, delta/wye connections, number of output ports, and power electronic converters. More than 250 published papers from the recent literature have been reviewed to identify the common understandings, practical implementation challenges, and research opportunities in the application of DC ultra-fast charging in EVs. In particular, the works published over the last three years about SST-based DC ultra-fast charging have been reviewed.

/pdf/review-of-solid-state-transformer-applications-on-electric-2uc05197.pdf

Review of Solid-State Transformer Applications on Electric Vehicle DC Ultra-Fast Charging Station

Chemical mechanical polishing (CMP) is a well-known technology that can produce surfaces with outstanding global planarization without subsurface damage. A good CMP process for Silicon Carbide (SiC) requires a balanced interaction between SiC surface oxidation and the oxide layer removal. The oxidants in the CMP slurry control the surface oxidation efficiency, while the polishing mechanical force comes from the abrasive particles in the CMP slurry and the pad asperity, which is attributed to the unique pad structure and diamond conditioning. To date, to obtain a high-quality as-CMP SiC wafer, the material removal rate (MRR) of SiC is only a few micrometers per hour, which leads to significantly high operation costs. In comparison, conventional Si CMP has the MRR of a few micrometers per minute. To increase the MRR, improving the oxidation efficiency of SiC is essential. The higher oxidation efficiency enables the higher mechanical forces, leading to a higher MRR with better surface quality. However, the disparity on the Si-face and C-face surfaces of 4H- or 6H-SiC wafers greatly increases the CMP design complexity. On the other hand, integrating hybrid energies into the CMP system has proven to be an effective approach to enhance oxidation efficiency. In this review paper, the SiC wafering steps and their purposes are discussed. A comparison among the three configurations of SiC CMP currently used in the industry is made. Moreover, recent advances in CMP and hybrid CMP technologies, such as Tribo-CMP, electro-CMP (ECMP), Fenton-ECMP, ultrasonic-ECMP, photocatalytic CMP (PCMP), sulfate-PCMP, gas-PCMP and Fenton-PCMP are reviewed, with emphasis on their oxidation behaviors and polishing performance. Finally, we raise the importance of post-CMP cleaning and make a summary of the various SiC CMP technologies discussed in this work.

Recent Advances In Silicon Carbide Chemical Mechanical Polishing Technologies

Energy band alignment of 2D/3D MoS2/4H-SiC heterostructure modulated by multiple interfacial interactions

Existing studies show that several performance issues will arise in the HVDC link during the three phase-to-ground fault at the side of the inverter and that the DC voltage will oscillate around zero and will not affect the rectifier of the AC system though the inverter of the AC system, and the AC voltages will become zero and the AC currents will show high amplitude as well as minor disturbances. It has also been argued that when the fault is applied on a single-phase to ground fault at the inverter side on the AC side, the voltage will decrease. In this paper, we focus on single line-to-ground fault, double line-to-ground fault, and three phase-to-ground fault at the inverter of the AC system and their behavior on the DC link as well as on the AC system of the rectifier with detailed simulations. A high voltage direct current (HVDC) Monopolar system is modeled using a Matlab/Simulink software package for the research. The results show that during the three phase-to-ground fault at the AC system of the inverter, the DC voltage will increase with a bogus waveform and the currents of the AC system at the rectifier will collapse to zero.At the double phase-to-ground fault level, the DC voltage will experience an increase in waveform while the currents of the AC system of the rectifier will experience different disturbances. At the single phase-to-ground fault level, the DC voltage will remain stable and the rectifier side of the AC system will also experience a stable state for both currents and voltages.

https://www.mdpi.com/2227-7390/10/16/3014/pdf?version=1661234706

Using Matlab/Simulink Software Package to Investigate Fault Behaviors in HVDC System

4H silicon carbide (4H‐SiC) holds great promise for high‐power and high‐frequency electronics, in which high‐quality 4H‐SiC wafers with both global and local planarization are cornerstones. Chemical–mechanical polishing (CMP) is the key processing technology in the planarization of 4H‐SiC wafers. Enhancing the performance of CMP is critical to improving the surface quality and reducing the processing cost of 4H‐SiC wafers. In this review, the superior properties of 4H‐SiC and the processing of 4H‐SiC wafers are introduced. The development of CMP with chemical, mechanical, and chemical–mechanical synergistic approaches to improve the performance of CMP is systematically reviewed. The basic principle and processing system of each improvement approach are presented. By comparing the material removal rate of CMP and the surface roughness of CMP‐treated 4H‐SiC wafers, the prospect on the chemical, mechanical, and chemical–mechanical synergistic improvement approaches is finally provided.

https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/admi.202202369

Chemical–Mechanical Polishing of 4H Silicon Carbide Wafers

Owing to the superior properties of silicon carbide (SiC), such as higher breakdown voltage, higher thermal conductivity, higher operating frequency, higher operating temperature, and higher saturation drift velocity, SiC has attracted much attention from researchers and the industry for decades. With the advances in material science and processing technology, many power applications such as new smart energy vehicles, power converters, inverters, and power supplies are being realized using SiC power devices. In particular, SiC MOSFETs are generally chosen to be used as a power device due to their ability to achieve lower on-resistance, reduced switching losses, and high switching speeds than the silicon counterpart and have been commercialized extensively in recent years. A general review of the critical processing steps for manufacturing SiC MOSFETs, types of SiC MOSFETs, and power applications based on SiC power devices are covered in this paper. Additionally, the reliability issues of SiC power MOSFET are also briefly summarized.

/pdf/review-of-silicon-carbide-processing-for-power-mosfet-dq8trzig.pdf

Kunghong Lee

Papers

Review of Silicon Carbide Processing for Power MOSFET