K
Kurt F. Baty
Publications - 9
Citations - 225
Kurt F. Baty is an academic researcher. The author has contributed to research in topics: Back-side bus & System bus. The author has an hindex of 5, co-authored 9 publications receiving 225 citations.
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Patent
Digital data processor apparatus with pipelined fault tolerant bus protocol
Gardner C. Hendrie,Kurt F. Baty,Ronald E. Dynneson,Daniel M. Falkoff,Robert Reid,Joseph E. Samson,Kenneth T. Wolff +6 more
TL;DR: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units as mentioned in this paper.
Patent
Digital data processor with high reliability
Joseph E. Samson,Kenneth T. Wolff,Robert Reid,Gardner C. Hendrie,Daniel M. Falkoff,Ronald E. Dynneson,Daniel M. Clemson,Kurt F. Baty +7 more
TL;DR: In this article, a fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units on a bus structure common to all the units.
Patent
Computer peripheral control apparatus
TL;DR: A fault-tolerant computer system as mentioned in this paper provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units on a bus structure common to all the units.
Patent
Optimized interconnect networks
TL;DR: Two-way and (n)-way interconnect arrays may be adapted for use in fault-tolerant communications as discussed by the authors, where the relationship between the number of independent buses (b), number of nodes (v), and the degree of interconnectedness (n) can be expressed by the equation.
Patent
Digital data processor with high reliability and method
Joseph E. Samson,Kenneth T. Wolff,Robert Reid,Gardner C. Hendrie,Daniel M. Falkoff,Ronald E. Dynneson,Daniel M. Clemson,Kurt F. Baty +7 more
TL;DR: A fault-tolerant computer system as discussed by the authors provides information transfers between the units of a computing module, including a processor unit and a memory unit, on a bus structure common to all the units.