Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

Backlight systems dominate the power requirements of battery-operated hand-held devices with color thin-film transistor (TFT), liquid crystal displays (LCDs). We introduce dynamic luminance scaling of the backlight with appropriate image compensation. Dynamic backlight luminance scaling (DLS) keeps the perceived intensity or contrast of the image as close as possible to the original while achieving significant power reduction. DLS compromises quality of image between power consumption, which fulfills a large variety of user preferences in power-aware multimedia applications. DLS saves 20% to 80% of power consumption of the backlight systems while keeping a reasonable amount of image quality degradation.

DLS: dynamic backlight luminance scaling of liquid crystal display

Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can potentially be off-set by thermal considerations which impact chip performance and reliability. The work presented in this paper is the first attempt to study the performance benefits of 3-D technology under the influence of such thermal constraints. Using a processor-cache-memory system and carefully chosen applications encompassing different memory behaviors, the performance of 3-D architecture is compared with a conventional planar (2-D) design. It is found that the substantial increase in memory bus frequency and bus width contribute to a significant reduction in execution time with a 3-D design. It is also found that increasing the clock frequency translates into larger gains in system performance with 3-D designs than for planar 2-D designs in memory intensive applications. The thermal profile of the vertically stacked chip is generated taking into account the highly temperature sensitive leakage power dissipation. The maximum allowed operating frequency imposed by temperature constraint is shown to be lower for 3-D than for 2-D designs. In spite of these constraints, it is shown that the 3-D system registers large performance improvement for memory intensive applications.

/pdf/a-thermally-aware-performance-analysis-of-vertically-1b09oowexp.pdf

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

An LCD (Liquid Crystal Display) is a standard display device for hand-held embedded systems. Today, color TFT (Thin-Film Transistor) LCDs are common even in cost-effective equipments. An LCD display system is composed of an LCD panel, a frame buffer memory, an LCD and frame buffer controller, and a backlight inverter and lamp. All of them are heavy power consumers, and their portion becomes much more dominant when running interactive applications. This is because interactive applications are often triggered by human inputs and thus result in a lot of slack time in the CPU and memory system, which can be effectively used for dynamic power management. In this paper, we introduce low-power LCD display schemes as a system-level approach. We accurately characterize the energy consumption at the component level and minimize energy consumption of each component without appreciable display quality degradation. We develop several techniques such as variable-duty-ratio refresh, dynamic-color-depth control and backlight luminance dimming with brightness compensation or contrast enhancement.

/pdf/low-power-color-tft-lcd-display-for-hand-held-embedded-3wn1orlxps.pdf

Low-power color TFT LCD display for hand-held embedded systems

Energy conservation in battery powered mobile devices that perform wireless multimedia streaming has been a significant research problem since last decade. This is because these mobile devices consume a lot of power while receiving, decoding and ultimately, presenting the multimedia content. What makes things worse is the fact that battery technologies have not evolved enough to keep up with the rapid advancement of mobile devices. This survey examines solutions that have been proposed during the last few years, to improve the energy efficiency of wireless multimedia streaming in mobile hand-held devices. We categorize the research work according to different layers of the Internet protocol stack they utilize. Then, we again regroup these studies based on different traffic scheduling and multimedia content adaptation mechanisms. The traffic scheduling category contains those solutions that optimize the wireless receiving energy without changing the actual multimedia content. The second category on the other hand, specifically modifies the content, in order to reduce the energy consumed by the wireless receiver and to decode and view the content. We compare them and provide evidence of the fact that some of these tactics already exist in modern smaprtphones and provide energy savings with real measurements. In addition, we discuss some relevant literature on the complementary problem of energy-aware multimedia delivery from mobile devices and contrast with our target approaches for multimedia transmission to mobile devices.

https://users.aalto.fi/~siekkine/pub/hoque12survey.pdf

Energy Efficient Multimedia Streaming to Mobile Devices — A Survey

We introduce an energy consumption analysis of complex digital systems through a case study of ARM7TDMI RISC processor by using a new energy measurement technique. We developed a cycle-accurate energy consumption measurement system based on charge transfer which is robust to spiky noise and is capable of collecting a range of power consumption profiles in real time. The relative energy variation of the RISC core is measured by changing the op-code, the instruction fetch address, the register number, the register value, the data fetch address, and the immediate operand value in each pipeline stage, respectively. We demonstrated energy characterization of a pipelined RISC processor for high-level power reduction.

/pdf/cycle-accurate-energy-consumption-measurement-and-analysis-4oan6zsr51.pdf

Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI

Energy characterization is the basis for high-level energy reduction. Measurement-based characterization is accurate and independent of model availability and is thus suitable for commercial off-the-shelf (COTS) components, but conventional measurement equipment has serious limitations in this context. We introduce a new technique for the energy characterization of a microprocessor using a cycle-accurate energy measurement system based on charge transfer which is robust to spiky noise and is able to collect a range of energy consumption profiles in real time. It measures the energy variation of the CPU core by changing the instruction-level energy-sensitive factors such as opcodes (operations), instruction fetch addresses, register numbers, register values, data fetch addresses and immediate operand values at each pipeline stage. Using the ARM7TDMI RISC processor as a case study, we observe that the energy contributions of most instruction-level energy-sensitive factors are orthogonal to the operations. We are able to characterize the energy variation, preserving all the effects of the energy-sensitive factors for various software methods of energy reduction. We also demonstrate applications of our measurement and characterization techniques.

Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors]

In this paper, we introduce a precise energy characterization of SDRAM main memory systems and explore the amount of energy associated with design parameters, leading to energy reduction techniques that we are able to recommend for practical use. We build an in-house energy simulator for SDRAM main memory systems based on cycle-accurate energy measurement and state-machine-based characterizations which independently characterize dynamic and static energy. We explore energy behavior of the memory systems by changing design parameters such as processor clock, memory clock and cache configuration. Finally we propose new energy reduction techniques for the address bus and practical mode control schemes for the SDRAM devices. We save 10.8 mJ and 12 mJ, 40.2% and 14.5% of the total energy, for 24 M instructions of an MP3 decoder and a JPEG compressor, using a typical 32-bit, 64 MB SDRAM memory system.

/pdf/energy-exploration-and-reduction-of-sdram-memory-systems-tqzm9ze145.pdf

Energy exploration and reduction of SDRAM memory systems

High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction techniques for memory systems deliberating on burst-mode transfers over the high-speed bus specifications such as Low Voltage BiCMOS (LVT), Gunning Transfer Logic (GTL+) and Stub Series Termination Logic (SSTL_2) which are widely used. The reduction techniques take both the static and the dynamic power consumption into account because most high-performance bus drivers and end-termination networks dissipate significant static power as well. Extensive performance analysis is conducted through mathematical analysis and trace data-driven simulations. We had reduction of 14% with random data and up to 67.5% with trace data.

/pdf/bus-encoding-for-low-power-high-performance-memory-systems-499neg1btb.pdf

Bus encoding for low-power high-performance memory systems

In this paper, we propose an energy-aware MPEG-4 FGS video streaming system with client feedback. In this client-server system, the battery-powered mobile client sends its maximum decoding capability (i.e., its decoding aptitude) to the server in order to help the server determine the additional amount of data (in the form of enhancement layers on top of the base layer) per frame that it sends to the client, and thereby, set its data rate. On the client side, a dynamic voltage and frequency scaling technique is used to adjust the decoding aptitude of the client while meeting a constraint on the minimum achieved video quality. As a measure of energy efficiency of the video streamer, the notion of a normalized decoding load is introduced. It is shown that a video streaming system that maintains this normalized load at unity produces the optimum video quality with no energy waste. We implemented an MPEG-4 FGS video streaming system on an XScale-based testbed in which a server and a mobile client are wirelessly connected by a feedback channel. Based on the actual current measurements in this testbed, we obtain an average of 20% communication energy reduction in the client by making the MPEG-4 FGS streamer energy-aware.

/pdf/energy-aware-mpeg-4-fgs-streaming-3stlklocn8.pdf

Kwanho Kim

Papers

Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI

Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors]

Energy exploration and reduction of SDRAM memory systems

Bus encoding for low-power high-performance memory systems

Energy-aware MPEG-4 FGS streaming