: The satisfiability (SAT) problem is a core problem in mathematical logic and computing theory. In practice, SAT is fundamental in solving many problems in automated reasoning, computer aided design, computer aided manufacturing, machine vision, database, robotics, integrated circuit design, computer architecture design, and computer network design. Traditional methods treat SAT as a discrete, constrained decision problem. In recent years, many optimization methods, parallel algorithms, and practical techniques have been developed for solving SAT. In this survey, we present a general framework (an algorithm space) that integrates existing SAT algorithms into a unified perspective. We describe sequential and parallel SAT algorithms including variable splitting, resolution, local search, global optimization, mathematical programming, and practical SAT algorithms. We give performance evaluation of some existing SAT algorithms. Finally, we provide a set of practical applications of the satisfiability problems.

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Algorithms for the Satisfiability (SAT) Problem: A Survey,

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.


Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly 
Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence 
Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products 
Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes



Table of Contents


Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

Electronic Design Automation: Synthesis, Verification, and Test

http://www.ee.umn.edu/users/sachin/jnl/integration01.pdf

A survey on multi-net global routing for integrated circuits

Rectilinear paths among rectilinear obstacles

This paper represents a fairly extensive survey of the literature on the interconnection problem. The topics covered are: Pin Assignment, Layering, Ordering, Wire List Determination, Spanning Trees, Rectilinear Steiner Trees and Wire Layout. In addition, several new ideas are presented which could provide for better wire layout. Algorithms are presented in a way that makes them easy to understand and hence, to discuss and apply. Formal statement of the algorithms can be found in the references cited.

The interconnection problem - a tutorial

Most wire-routing programs utilize a maze-running technique to route one connection at a time. Once routed, a wire cannot be moved even if it is subsequently discovered to interfere with the successful completion of other connections. The order in which the desired connections are presented to the routing algorithm has therefore been thought to be of critical importance. Experimental evidence is presented, however, to show that the performance of a router, when measured in terms of the total of the minimum (or ideal) lengths of the connections successfully completed, is, in fact, independent of the order in which connections are attempted.

L.C. Abel

Papers

On the Ordering of Connections for Automatic Wire Routing