In this paper, a fast transient testing methodology for predicting the performance parameters of analog circuits is presented. A transient test signal is applied to the circuit under (cut) test and the transient response of the circuit is sampled and analyzed to predict the circuit's performance parameters. An algorithm for generating the optimum transient test signal is presented. The methodology is demonstrated in a production environment using a low-power opamp. Result from production test data showed: 1) a ten times speedup in production testing; 2) accurate prediction of the performance parameters; and 3) a simpler test configuration.

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Prediction of analog performance parameters using fast transient testing

Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

A tutorial introduction to research on analog and mixed-signal circuit testing

Analog testing is a difficult task without a clearcut methodology. Analog circuits are tested for satisfying their specifications, not for faults. Given the high cost of testing analog specifications, it is proposed that tests for analog circuits should be designed to detect faults. Therefore analog fault modeling is discussed. Based on an analysis of the types of tests needed for different types of faults, algorithms for fault-driven test set selection are presented. A major reduction in testing time should come from reducing the number of specification tests that need to be performed. Hence algorithms are presented for minimizing specification testing time. After specification testing time is minimized, the resulting test sets are supplemented with some simple, possibly non-specification, tests to achieve 100% fault coverage. Examples indicate that fault-driven test set development can lead to drastic reductions in production testing time. >

Minimizing production test time to detect faults in analog circuits

An approach based on functional testing and on sensitivity calculation of many output parameters for diagnosis of defective elements in analog circuits is presented. A sensitivity matrix that gives the relation between the deviation of output parameters and the deviation of defective components in a circuit forms the basis of the test equations. Diverse types of measurement help improve the diagnostic resolution. Experimental results are presented to clarify the algorithm and prove its efficiency in a practical case. >

Analog circuit fault diagnosis based on sensitivity computation and functional testing

A new low-cost test method for analog integrated circuits, called oscillation-test, is presented. During the test mode, the circuit under test (CUT) is converted to a circuit that oscillates. Faults in the CUT which cause a reasonable deviation of the oscillation frequency from its nominal value can be detected. Using this test method, no test vector is required to be applied. Therefore, the test vector generation problem is eliminated and the test time is very small because a limited number of oscillation frequencies is evaluated for each CUT. Due to its digital nature, the oscillation frequency can be easily interfaced to boundary scan. This characteristics imply that oscillation-test strategy is very attractive for wafer-probe testing as well as final production testing. In this paper, the validity of the proposed test method has been verified throughout some examples such as operational amplifiers and analog-to-digital converter (ADC).

Oscillation-test strategy for analog and mixed-signal integrated circuits

Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage. >

https://www.computer.org/csdl/pds/api/csdl/proceedings/download-article/12OmNx7XH2g/pdf

Optimal test set design for analog circuits

An algorithm for computing parametric yield is presented. The algorithm uses statistical modeling techniques and takes advantage of incremental knowledge of the problem to reduce significantly the number of simulations needed. Polynomial regression is used to construct simple equations mapping parameters to measurements. These simple polynomial equations can then replace circuit simulations in the Monte Carlo algorithm for computing parametric yield. The algorithm differs from previous statistical modeling algorithms using polynomial regression for three major reasons: first, the random error that is postulated in polynomial regression equations is taken into account when computing parametric yield; second, the variance of the yield is computed; and third, the algorithm is fully automated. Therefore a direct comparison with Monte Carlo methods can be made. Examples indicate that significant speed-ups can be attained over Monte Carlo methods for a large class of problems. >

L. Milor

Papers

Minimizing production test time to detect faults in analog circuits

Optimal test set design for analog circuits

Computing parametric yield accurately and efficiently