Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Understanding Delta-Sigma Data Converters

Nanofabrication of magnetic storage media, where servo marks, discrete tracks or individual islands are defined, offer the prospect for improved performance and increased areal density. However, this increase in performance will require that new and additional processes be introduced into disk manufacturing. We review here the fundamental patterning and fabrication processes that have been proposed, along with their respective strengths and weaknesses and the potential advantages they may offer for magnetic recording. The increase in data density afforded by nanofabrication may have added significance as more conventional approaches to ever increasing density will encounter physical limitations set by the thermal stability of the recorded bits.

https://iopscience.iop.org/article/10.1088/0022-3727/38/12/R01/pdf

Nanofabricated and self-assembled magnetic structures as data storage media

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

/pdf/computer-aided-design-of-analog-and-mixed-signal-integrated-23xbvj9rc2.pdf

Computer-aided design of analog and mixed-signal integrated circuits

We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

/pdf/optimal-design-of-a-cmos-op-amp-via-geometric-programming-4thsejbwi6.pdf

Optimal design of a CMOS op-amp via geometric programming

Analog circuit synthesis entails the creation of both the topology and the sizing (numerical values) of all of the circuit's components. This paper presents a single uniform approach using genetic programming for the automatic synthesis of both the topology and sizing of a suite of eight different prototypical analog circuits, including a low-pass filter, a crossover filter, a source identification circuit, an amplifier, a computational circuit, a time-optimal controller circuit, a temperature-sensing circuit, and a voltage reference circuit. The problem-specific information required for each of the eight problems is minimal and consists of the number of inputs and outputs of the desired circuit, the types of available components, and a fitness measure that restates the high-level statement of the circuit's desired behavior as a measurable mathematical quantity. The eight genetically evolved circuits constitute an instance of an evolutionary computation technique producing results on a task that is usually thought of as requiring human intelligence.

/pdf/automated-synthesis-of-analog-electrical-circuits-by-means-4u553mzer4.pdf

Automated synthesis of analog electrical circuits by means of genetic programming

A hierarchically structured framework for analog circuit synthesis is described. This hierarchical structure has two important features: it decomposes the design task into a sequence of smaller tasks with uniform structure, and it simplifies the reuse of design knowledge. Mechanisms are described that select from among alternate design styles and translate performance specifications from one level in the hierarchy to the next lower, more concrete level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers from performance specifications and process parameters. Measurements from detailed circuit simulation and from actual fabricated analog ICs based on OASYS-synthesized designs demonstrate that OASYS is capable of synthesizing functional circuits. >

OASYS: a framework for analog circuit synthesis

An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from performance specifications and process parameters, and demonstrates the workability of the approach.

/pdf/a-prototype-framework-for-knowledge-based-analog-circuit-2syu7mxh48.pdf

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis

Built-in current (BIC) testing involves the monitoring of power bus currents in a VLSI circuit, as a means of detecting processing defects in the circuit. The design and performance of a prototype BIC sensor for static CMOS are discussed. It has been demonstrated that a fully-operational BIC sensor can be designed using a standard CMOS process. The presented design met all basic requirements: it was small, it caused only a small degradation of the performance of the monitored module, and it provided sufficient current resolution. The main disadvantage of the described design, however, was a substrate current caused by the structure of the bipolar transistor. >

Current sensing for built-in testing of CMOS circuits

ANAGRAM models cell layout in the style of a macrocell place-and-route problem. Individual cell primitives (transistor-level objects of widely varying sizes) are the macrocells. Module generation techniques are used to generate these internal primitives and to preserve critical matching and symmetries. An annealing-based placement algorithm then places these primitives. This is followed by a novel line-expansion signal router, which includes mechanisms to avoid noise coupling due to internodal capacitances between the signal wires and shared parasitic resistances in the DC supply wiring and operates in an iterative improvement fashion to eliminate such violations. Layouts for several custom CMOS cells have been successfully generated. Circuit-simulation results based on cell extractions demonstrate the effectiveness of the crosstalk-avoidance mechanisms. >

Automatic layout of custom analog cells in ANAGRAM

A 16-bit oversampling D/A (digital-to-analog) converter has been designed using a fourth-order all-digital noise-shaping loop followed by a 3-bit D/A converter. The 3-bit D/A converter, which uses a novel form of dynamic element matching achieves high accuracy and long-term stability without requiring precision matching of components. The harmonic distortion of the untrimmed monolithic CMOS prototype D/A converter is less than -90 dB. This converter achieves performance comparable to that of a 1-bit noise-shaping D/A that operates at nearly four times its clock rate. >

L.R. Carley

Papers

OASYS: a framework for analog circuit synthesis

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis

Current sensing for built-in testing of CMOS circuits

Automatic layout of custom analog cells in ANAGRAM

A 16-bit 4'th order noise-shaping D/A converter