An approach to modular and hierarchical sequential circuit test generation, which exploits a top-down design methodology, uses high level test knowledge and constraint driven module test generation to target faults at the structural level, is introduced in this paper. Results obtained for several designs are provided to demonstrate the effectiveness of our approach and the need for high level knowledge along with global constraints while deriving sequential circuit tests. >

CHEETA: Composition of hierarchical sequential tests using ATKET

Macro Testability; The Results of Production Device Applications

The authors describe the design and implementation of SYNTEST, a system for the design of self-testable VLSI circuits from behavioral description. SYNTEST consists of several algorithmic synthesis tools for scheduling, testable allocation, and optimum test points selection. A key feature in SYNTEST is the tight interaction between the system tools: the scheduler, the allocator, and the test tool. The system uses a technology library for optimizing the original structure. All tools interact with each other as well with the user through an X graphical interface. This provides a better design environment and allows for more designer intervention. >

SYNTEST: an environment for system-level design for test

Testing of embedded cores poses a great challenge. These cores cannot be tested in isolation because core I/Os are not directly accessible from ASIC I/Os. A novel test methodology is developed which generates a partial netlist for protection of intellectual property (IP) by performing structural analysis. This partial netlist is used in ASIC level test generation. For the remaining gates of the core, patterns are supplied to test those gates, which can be applied through only core scan chain. Another scheme is developed to select a few I/Os optimally to add boundary scan circuits to improve IP protection.

Test methodology for embedded cores which protects intellectual property

A novel scan path design technique is presented, which facilitates the application of two-pattern tests by transition shifting. The scan path is composed based on the test data set as a graph matching problem. For the reduction of the required test application time, a novel reconfigurable scan path architecture is presented, which is synthesized based on the test data set. This reconfigurable scan path concept is applicable not only to two-pattern test sets but also when the test program has been generated for stuck-at faults. >

On scan path design for stuck-open and delay fault detection

A novel incremental procedure for the hierarchical assembly of macro test specifications into a chip test program is presented. To solve test generation/application problems, a bottom-up symbolic test assembly procedure that proceeds in line with the construction of the system is proposed. It is shown that for a modular design approach, this procedure can be extended with design-for-testability features to ensure that all macro tests are assembled into a chip test program. The approach is exemplified by the design of a decimation filter for a Sigma / Delta A/D (analog-to-digital) converter. >

L. Spaanenburg

Papers

Hierarchical test assembly for macro based VLSI design