A method for fault detection probability estimation using statistical multi-parameter circuit simulation is proposed, in order to check circuits for which double or multiple analogue measurements are utilized. Theoretical analysis for the estimation of the fault coverage is given, based on conditional probability calculations. The proposed method can be applied for both test measurement and input stimulus selection. Simulation results from the application of the method on typical analogue circuits—filter and amplifier—are given, showing a sufficient improvement over the fault coverage achieved by single measurements. Copyright © 2009 John Wiley & Sons, Ltd.

Improved analogue fault coverage estimation using probabilistic analysis

Automatic Test Equipment (ATE) has been traditionally tasked with supporting field returns. This task includes verification of proper operation and in the alternative to diagnose and provide repair instructions. While ATE has done reasonably well to certify a unit under test as ready for issue (RFI), it has been hampered by diagnostic complications in many instances. Two such complications, Cannot Duplicates (CNDs) and Retest OKs (RTOKs) are particularly troublesome because of the ATEpsilas limited vocabulary of Pass/Fail or Good/Bad determination. When a unit under test (UUT) is returned from the field labeled faulty, yet passes on the ATE, a RTOK, additional testing and diagnosis is required, despite the ldquoPassrdquo result. Similarly, when multiple runs on an ATE provide different results, a CND, the ATE (in conjunction with the test program set -TPS) is not sufficient to unravel the conflict. In such instances, the ATE must be supplemented with various tools that characterize the physics of the circuit in order to assist in diagnoses. This paper will highlight a number of failure modes that can create CND and RTOK, and examine tools that can be used instead of or in conjunction with ATE to help diagnose and repair units that experience such phenomenon.

Unraveling the Cannot Duplicate and Retest OK problems by utilizing physics in testing and diagnoses

Design for Testability (DFT) evaluation is quite complex and circuit dependent. To simplify the analysis and to apply the methodology more generally to different circuit types and different levels of assembly, we focus our efforts on identifying areas of poor testability. We introduce metrics we call Sensitized Path Oriented Testability Scoring ™ or SPOTS ™, performed at all points where failure modes are to be detected and diagnosed, to spot poor testability. Once the problem is identified early in the design stage, especially when it is correlated with a circuit node and a failure mode, the remedy needed to correct the problem through DFT can be quite practical. SPOTS measures four testability attributes - controllability, distinguishability, test resource costs, and test escapes due to lack of testability. The metrics simplify previous testability techniques, by utilizing sensitized paths to measure circuit controllability. The use of sensitized paths greatly reduces the analysis required, and while it may not offer validation of testability, it succeeds in highlighting areas that lack testability. Controllability metric (CM) provides a number corresponding to the number of steps required to sensitize a path. Distinguishability metric (DM) measures the difficulty of isolating one fault from others. Test resource cost (RC), includes test program set (TPS) development costs and test equipment requirements, and is expressed in monetary currency. Penalty cost (PC) measures in currency the cost incurred for nodes left untested by escaping detection in tests. Associating each of these metrics to failure modes at each node creates a table that reveals where testability problems exist. Designers and testability analysts can work together to resolve them either by altering the fault detection and isolation requirements, improving test resources and/or redesigning the unit under test (UUT). This form of analysis is simpler to use and is applicable to any level of assembly — IC, board or system. It can even be utilized by those procuring commercial off the shelf (COTS) products to compare support costs for competing products.

Simplified metrics for evaluating designs for testability

There is a phenomenon which exists in complex engineered systems, most notably those which are electrical or electronic which is the inability to diagnose faults reported during operation. This includes difficulties in detecting the same reported symptoms with standard testing, the inability to correctly localise the suspected fault and the failure to diagnose the problem which has resulted in maintenance work. However an inconsistent terminology is used in connection with this phenomenon within both scientific communities and industry. It has become evident that ambiguity, misuse and misunderstanding have directly compounded the issue. The purpose of this paper is to work towards standardisation of the taxonomy surrounding the phenomena popularly termed No Fault Found, Retest Okay, Cannot Duplicate or Fault Not Found amongst many others. This includes discussion on how consistent terminology is essential to the experts within organisation committees and, to the larger group of users, who do not have specialised knowledge of the field.

No fault found, Retest ok, Cannot duplicate or fault not found? Towards a standardised taxonomy

Design for testability (DFT) has been accepted as a cost saving approach in many applications. The rationale has been demonstrated in several papers by calculations showing how DFT benefits derived outweigh costs. In those cases benefits dealt with cost savings in producing, testing and deploying a product. Apparently, such benefits are bound by an upper limit as the savings could not be greater than the cost of making the product. In this paper, however, we model the revenue generation capability of a product through its life cycle and demonstrate that the impact on profits by poor quality products can be much greater. DFT can mitigate many of the causes for poor quality products. We provide examples of recent economic harm and disaster caused by defective electronics. For these examples we postulate what DFT could have done to mitigate the defects and how much money the companies could have saved if DFT prevented the problems. Benefits derived from DFT in the product life cycle combines with traditionally demonstrated DFT benefits in production, making DFT even more compelling.

The economics of harm prevention through Design for Testability

In this paper, we will define some of the terminology, provide a model for the diagnostic process, and highlight areas of diagnostic complications. We will apply the diagnostic complications in a Venn diagram to get a better illustration and possibly create a basis for diagnosability metrics in future work. With the tools at hand, we will finally tackle the design issues by hypothesizing on various causes of each diagnostic complication and providing some (though not exhaustive) DFD guidelines.

Design for Diagnosability Guidelines

The concept of design for diagnosability (DfD) is introduced as a different concept than design for testability (DfT). Separating design for diagnosability guidelines from those of the more general design for testability guidelines enables circuit designers to distinguish between those guidelines that separate good circuits from faulty ones and guidelines that are aimed at improving the repair process. Comprehensive fault detection does not result in cost effective repair without unambiguous fault isolation. A model is used to demonstrate the distinctions between test and diagnostic goals. Diagnoses related terminology is introduced and diagnostic complications are discussed. Hidden faults, cannot duplicates (CNDs), retest OK, fault isolation ambiguity, false remedies and false alarms are explored in great detail. A Venn diagram model is used to further explain Diagnosability and the diagnostic complications. The term Distinguishability is added to our vocabulary as the positive dual of ambiguity. The paper probes the possible causes of the various diagnostic issues and provides guidelines designers can incorporate to eliminate them. The paper offers specific design guidelines to achieve a more diagnosable or diagnostic-friendly circuit design. In doing so, diagnostic complications can be reduced, resulting in lower cost repairs and maintenance.

L.Y. Ungar

Papers

Design for Diagnosability Guidelines

Design for diagnosability guidelines