A parallel associative memory provides a way of recognizing or identifying observed data patterns. Each of a plurality of memories stores a plurality of recognition patterns. In response to receipt of a recall pattern to be identified, the recall pattern is contemporaneously compared to the recognition patterns stored in the memories and an exact or best match recognition pattern is selected. In a preferred embodiment, the memories may store multiple data bases each of which includes patterns having different lengths and different radii of attraction. The comparison process is controlled by masks which specify respective portions of the patterns which may include the radii of attraction, bits which must identically match, bits which are ignored, bits which are compared in a bit-wise fashion, and bytes which are compared by multiplication. A correlation is computed and selectively adjusted by the respective radii of attraction. A specified number of the patterns having the best correlation are identified, subject to selected threshold conditions, and sorted according to their respective correlations. The parallel nature of the memory lends itself to a hierarchical organization for increased storage capacity and to parallel processing which increases the speed of the identification or recognition process and thereby allows a broad range of applications. These applications includes fast retrieval of exact or inexact data, diagnosis, image processing and speech recognition.

Parallel associative memory having improved selection and decision mechanisms for recognizing and sorting relevant patterns

Various possible implementation schemes for concurrent programming concepts are surveyed. Based upon this examination, computer design features are proposed which assist in the efficient realization of concurrent programming concepts in a multiprocessor machine which is constructed from a number of self-contained processors, each with its own random access memory. It is indicated how the proposed architecture provides hardware support for creating and terminating parallel execution paths. The hardware supports scheduled sharing of resources as its basic design feature. In particular, the problem of implementing scheduled waits in monitors is examined in detail. This is done in an environment where processes distributed among several physical processors are using a common monitor. It is also shown how the practical aspects of error resynchronization can be handled efficiently.

Hardware support for concurrent programming in loosely coupled multiprocessors

The discriminating content addressable memory (DCAM) is a modified content addressable memory (CAM). After the ``similar to'' search performed by the CAM, the modified memory searches in parallel for the highest value in a particular field across all words of the memory. Applications of DCAM can greatly speed up queue searches and scheduling processes in operating systems. Worst case DCAM query time for 1000 words is 2 ?s. The number of extra gates required by a DCAM increases linearly with memory size.

Larry D. Wittie

Papers

Memory Hardware for High Speed Job Selection