Showing papers by "Lars Hedrich published in 2001"
01 Jan 2001
TL;DR: In this chapter, algorithms for formal verification of analog systems circuits are presented and an algorithm for generating transient stimuli is outlined to help the designer finding the design flaws with well known transient simulations.
Abstract: In this chapter, algorithms for formal verification of analog systems circuits are presented. The algorithms compare two system descriptions on different levels of abstraction. They prove/disprove, that the systems have functionally similar inputoutput behavior. Additionally, in case of nonlinear dynamic circuits, an algorithm for generating transient stimuli is outlined to help the designer finding the design flaws with well known transient simulations. Some examples show the feasibility of the approaches.
15 citations