Showing papers by "Lars Hedrich published in 2008"
10 Mar 2008
TL;DR: A new analog specification language (ASL) for efficient property specifications is defined and model checking algorithms for implementing this language are presented and this allows verification of complex static and dynamic circuit properties that have not yet been formally verifiable with previous approaches.
Abstract: In this contribution an advanced methodology for model checking of analog systems is introduced. A new Analog Specification Language (ASL) for efficient property specifications is defined and model checking algorithms for implementing this language are presented. This allows verification of complex static and dynamic circuit properties like Oscillation and Startup Time that have not yet been formally verifiable with previous approaches. The new verification methodology is applied to example circuits and experimental results are discussed and compared to conventional circuit simulation.
42 citations
21 Jan 2008
TL;DR: In this article, a symbolic model checker (MScheck) for mixed-signal circuits is proposed. But the verification procedure is restricted to phase-locked loops, and the implementation of MScheck is not yet complete.
Abstract: In this paper we firstly introduce a novel symbolic model checker (MScheck) for mixed-signal circuits. MScheck is capable to conflate the continuous behavior, typical for analog designs, and the discrete behavior in the digital domain for formal verification. Timing information of both systems will be symbolically stored within multi terminal binary decision diagrams (MTBDDs) for the entire verification procedure. The effectiveness of our approach is demonstrated on a phase locked loop (PLL) by formal verification of the locking property1.
6 citations
TL;DR: This work improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties in a new assertion-based verification flow for designing mixed-Signal circuits.
Abstract: Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.
4 citations
10 Mar 2008
TL;DR: This paper presents a method towards automatic structural synthesis of analog multiplier based on a hierarchical topology "super-topology", which is abstracted from the most standard four-quadrant multipliers.
Abstract: This paper presents a method towards automatic structural synthesis of analog multiplier based on a hierarchical topology "super-topology", which is abstracted from the most standard four-quadrant multipliers. The essential components in the super-topology are four identical cells, which consist of several MOS-transistors and determine features and performances of multipliers. We build all possible cells within 3 transistors. Experimental results present three new multiplier structures with simulation results to show the creativity of our method.