A method is provided of delivering advertising items to a client at a portable device. A client ID is sent to a host server. A downloaded advertising item is produced relative to a product or service from the host server. The downloaded advertising item is parsed and stored. In response to the parsing and storing, displaying the advertising item is displayed to the client at the mobile device.

Delivering targeted advertising to mobile devices

A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

Data processing device and method

A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation. Further, activity counters may be selectively enabled for specific tasks in order to obtain more accurate profile information.

Temperature field controlled scheduling for processing systems

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Data processing method and device

The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

System and method for a cache in a multi-core processor

A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (μTLB) is associated with each resource that can initiate a memory transfer. The L2 cache, along with all of the TLBs and μTLBs have resource ID fields and task ID fields associated with each entry to allow flushing and cleaning based on resource or task. Configuration circuitry is provided to allow the digital system to be configured on a task by task basis in order to reduce power consumption.

Multiple microprocessors with a shared cache

A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic may comprise the inclusion of monitoring code that determines a performance characteristic associated with the instruction or a change in the instruction's operation (e.g., the inclusion of read or write barrier operations to support a garbage collector).

Dynamically changing the semantic of an instruction

A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory. The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory. The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory . The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.

Cache with multiple fill modes

A DSP (10) accesses internal memory using physical addresses and has a internal MMU (19) which allows the DSP (10) to work with a large virtual address space mapped to an external memory (20). The MMU (19) performs the translation between a virtual address and the physical address associated with the external memory (20). The MMU (19) includes a translation lookaside buffer (28) and walking table logic (32) for translating virtual addresses to physical addresses.

Digital signal processor with direct and virtual addressing

A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity with corresponding tag arrays ( 502 ( n )), four segments per entry and four valid and dirty bits. Each tag entry ( 1236 ) includes task-ID qualifier field ( 522 ) and a resource ID qualifier field ( 520 ). Data is loaded into various of lines ( 506 ) in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag ( 1236 ) associated with the data line is set to a valid state ( 526 ). In addition to setting a tag to a valid state, qualifier values are stored in qualifier fields ( 520, 522 ) in the tag. Each qualifier value specifies a usage characteristic of data stored in an associated data line of the cache. In response to an operation command ( 1251 ), each tag in the array of tags that contains a specified qualifier value is modified ( 1258 ) in accordance with the operation command. Various types of operation commands can be included in an embodiment of the invention, such as clean, flush, clean-flush, lock, and unlock, for example.

Lasserre Serge

Papers

Multiple microprocessors with a shared cache

Dynamically changing the semantic of an instruction

Cache with multiple fill modes

Digital signal processor with direct and virtual addressing

Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding to a qualifier field