Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about 1.66 Gb/s at Eb/N0=4.25 dB (a bit error rate of 10-8). It provides decoding performance within 0.5 and 0.25 dB of the floating-point sum-product algorithm with 32 and 16 iterations, respectively, and similar error-floor behavior. The decoder uses less than 40% of the lookup tables, flip-flops, and IO ports available on the FPGA device. The results provided in this paper validate the potential of stochastic LDPC decoding as a practical and competitive fully parallel decoding approach.

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Fully Parallel Stochastic LDPC Decoders

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Low density parity check decoder for regular LDPC codes

A grouped-parallel low-density parity-check (LDPC) decoder is designed for the (2048,1723) Reed-Solomon-based LDPC (RS-LDPC) suitable for 10GBASE-T Ethernet. A two-step decoding scheme reduces the wordlength to 4 bits while lowering the error floor to below 10-14 BER. The proposed post-processor is conveniently integrated with the decoder, adding minimal area and power. The decoder architecture is optimized by groupings so as to localize irregular interconnects and regularize global interconnects and the overall wiring overhead is minimized. The 5.35 mm2, 65 nm CMOS chip achieves a decoding throughput of 47.7 Gb/s. With scaled frequency and voltage, the chip delivers a 6.67 Gb/s throughput necessary for 10GBASE-T while dissipating 144 mW of power.

An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors

This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders amenable to low-voltage and low-power operation. First, a highly-parallel decoder architecture with low routing overhead is described. Second, we propose an efficient method to detect early convergence of the iterative decoder and terminate the computations, thereby reducing dynamic power. We report on a bit-serial fully-parallel LDPC decoder fabricated in a 0.13-mum CMOS process and show how the above techniques affect the power consumption. With early termination, the prototype is capable of decoding with 10.4 pJ/bit/iteration, while performing within 3 dB of the Shannon limit at a BER of 10-5 and with 3.3 Gb/s total throughput. If operated from a 0.6 V supply, the energy consumption can be further reduced to 2.7 pJ/bit/iteration while maintaining a total throughput of 648 Mb/s, due to the highly-parallel architecture. To demonstrate the applicability of the proposed architecture for longer codes, we also report on a bit-serial fully-parallel decoder for the (2048, 1723) LDPC code in 10 GBase-T standard synthesized with a 90-nm CMOS library.

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Power Reduction Techniques for LDPC Decoders

An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.

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An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

A CODEC fully compliant to DVB-S2 broadcast standards is implemented in both 013 /spl mu/m 8M and 90nm 7M low-leakage CMOS technologies The system includes encoders and decoders for both LDPC codes and serially concatenated BCH codes This CODEC outperforms the DVB-S2 error performance requirements by up to 01dB The 013 /spl mu/m design occupies 496mm/sup 2/ and operates at 200MHz, while the 90nm design occupies 158mm/sup 2/ and operates at 300MHz

A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes

The design of a full broadcast + interactive services compliant 2nd generation satellite digital video broadcast (DVB-S2) codec is presented.

A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices

The metrics matrix may include at least one particular layer including at least one particular column having several metrics cues, respectively, situated in different rows. For the particular layers the updating of the channel cue is associated with the particular column involving at each iteration one updated metric cue selected from all the metrics cues of the particular column. The row of the selected metric cues may change at each iteration.

Method and device for layered decoding of a succession of blocks encoded with an LDPC code

The implementation of a 350 Mb/s 16-state SISO turbo decoder and its corresponding coder are described. It performs within 1.8 dB of Shannon's limit in terms of error correction. Implemented in 0.13 /spl mu/m low-leakage technology, this codec occupies 10 mm/sup 2/ and is designed using a Matlab-to-RTL design flow.

A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder

A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Laurent Paumier

Papers

A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes

A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices

Method and device for layered decoding of a succession of blocks encoded with an LDPC code

A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder

Iterative decoding of a frame of data encoded using a block coding algorithm