This article presents an overview of current 16- and 32-bit microprocessor architectures that support memory management. The authors define the basic requirements for a processor to support memory management and introduce hierarchically organized memory. They describe several address translation schemes, such as paging, segmentation, and combined paging/segmentation and discuss their implementation in current microprocessors. They give special emphasis to the application of associative cache memory, and analyze and compare single-level and multi-level address mapping schemes. Futhermore, the article discusses the capabilities of current microprocessors to support virtual memory, which includes abilities to recognize an address fault, to abort the execution of the current instruction and save necessary information, and to restore the saved state and resume normal processing. The authors evaluate two methods to restart the interrupted instruction, instruction restart and instruction continuation, and discuss their implementation in current microprocessors. They also discuss protection and security issues, and evaluate two protection schemes, hierarchical and nonhierarchical.

A Survey of Microprocessor Architectures for Memory Management

During the first twelve years of their existence, microprocessors have evolved at a dramatic pace in terms of numbers, technology, power, functionality, and applications. This paper begins with a technical explanation of key microprocessor specifications. Four generations of microprocessors are considered in detail, along with case studies of popular chip families. Special-purpose processors, software issues, and performance evaluation techniques are other areas of discussion. Overall industry trends are presented.

Microprocessors&#8212;The first twelve years

An Architecture and an Interconnection Scheme for Time-Sliced Buses in Real-Time Processing.

General addressing mechanisms for microprocessors

The article proposes a new Tree-Structured-Architecture (TSA). The TSA is object-oriented, implements the notions of capability-based-addressing and the single-level-store, and it is particularly designed to narrow the semantic gap. It encourages modular programming and directly supports the concepts of tasks and inter-task communication, making it particularly suitable for multiprocessing and multiprogramming implementation.The TSA is implemented on a multi-resource, distributed, matrix-structured, reconfigurable, fault-tolerant computing system, proposed in this article. The system implements some ideas of the dynamic and the flexible architecture. The system possesses a high degree of regularity by implementing large amounts of identical units. The hardware is modular, permitting the addition or removal of groups of units, without a change in the system's software.

A Tree Structured Architecture for semantic gap reduction

and slave processors, this group of microprocessors addresses a wide range of system applications. When LSI/MOS chips were first developed, it was possible for designers to place approximately 1000 active elements on a single chip. Now, ten years later, the number of active elements per chip has risen to over 100,000. As we enter the second decade of LSI/MOS technology, applications for its use are continually expanding as the computational power of newly developed 16-and 32-bit microprocessors approaches that of mainframe computers. In short, microprocessor designers have their work cut out for them. Currently, software development efforts are becoming responsible for ever larger shares of product development costs. To offset these costs, microcomputer designers are shifting toward high-level language programming. Increasingly , users expect microprocessors to provide a cost-effective solution for HLL support with minimal degradation in overall system performance; this sets tougher requirements for microprocessor designers. Sophisticated future systems will require a combination of capabilities. Anticipating these needs, National Semiconductor has developed the NS 16000 microprocessor family to incorporate various architectural features into a new generation of devices. Utilizing National Semiconductor's XMOS technology, the design of the NS16000 family is implemented with 3.5-micron gate technology. This allows for a smaller die size, leading to a reduction in chip cost. The design challenges in creating this new family were met only after thoroughly considering market requirements and LSI technology limitations. This article describes some of the capabilities provided by the NS16000 architecture.

Lavi

Papers

The NS16000 Family-Advances in Architecture and Hardware