Lawrence C. Stewart

TL;DR: The goals, architecture, implementation and performance analysis of the Firefly are described, some measurements of hardware performance are presented, and the degree to which SRC has been successful in producing software to take advantage of multiprocessing is discussed.

TL;DR: In this paper, a packet routing scheme is proposed to enable multiple packets to be routed simultaneously through a mesh-connected network, where the routing mask includes a broadcast bit and the packet must be simultaneously routed to all of the output links specified by the mask.

TL;DR: Digital’s first RISC system built using the 64-bit Alpha AXP architecture is the prototype known as the Alpha demonstration unit or ADU, which consists of a backplane containing 14 slots, each of which can hold a CPU module, a 64MB storage module, or a module containing two 50MB/s I/O channels.

TL;DR: The Alpha Demonstration Unit (ADU) as mentioned in this paper is the prototype of the first 64-bit ADU, which was built within Digital to accelerate software development and early chip testing.