A disk drive is disclosed comprising a disk, a head for writing data to the disk, and control circuitry coupled to the head, the control circuitry comprising a signal amplifier outputting a first signal comprising an offset voltage, the control circuitry operable to determine a state signal based on comparing the first signal to a reference signal, increase a M-bit digital count value in response to a first state of the state signal, decrease the M-bit digital count value in response to a second state of the state signal, and determine a first analog signal based on N bits of the digital count value, wherein the first analog signal adjusts the offset voltage and M>N.

Continuous digital offset cancellation

A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The programmable array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the programmable blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.

Programmable microcontroller architecture(mixed analog/digital)

Switching regulator circuits and methods are provided for regulating output voltage that include an adjustable minimum peak inductor current level and adjustable burst comparator hysteresis for Burst Mode operation in switching regulators. Control over minimum peak inductor current level and burst comparator hysteresis is achieved during Burst Mode operation by allowing external user control of the burst threshold level and the burst comparator hysteresis. A single user-accessible input pin, two user-accessible input pins, or three user-accessible input pins may be used to distinguish between forced continuous and Burst Mode operations, set a burst threshold level, and set a burst comparator hysteresis during Burst Mode operation. The present invention may be applied to buck, boost, buck-boost, or any other suitable regulator circuit configuration. The present invention also may be employed with synchronous and non-synchronous switching regulators.

Circuits and methods for adjustable peak inductor current and hysteresis for burst mode in switching regulators

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Microcontroller Programmable System on a Chip

A method and a system for using a graphics user interface for programming a microcontroller The microcontroller design system includes a device editor system with integrated datasheet information and having three independent, but integrated workspaces to provide a programmer an organized way of displaying device editor information The three workspaces include a user module selection workspace, a user module placement workspace and a user module pin out workspace for allowing the programmer to select desired function components for a target microcontroller device The user module selection workspace allows the programmer to select desired components from a list of user modules and the placement workspace allows user modules to be placed in allowable hardware resources The user module pin out workspace provides the programmer with the means to retrieve pin out information on the selected user modules that constitute the desired target microcontroller device design

Method and system for using a graphics user interface for programming an electronic device

A configurable operational amplifier (200) which is programmed to specific characteristics and parameters for various requirements in the measurement of analog signals. These programmable characteristics and parameters are gain bandwidth product (GBWP), selection of operational amplifier (op-amp) or comparator modes of operation, input offset zero calibration, ultra low bias current, rail-to-rail input operation, and rail-to-rail output operation. The configurable operational amplifier (200) is used in combination with a microcontroller system (102), and may be fabricated on an integrated circuit die or in a multi-chip package.

Configurable operational amplifier as a microcontroller peripheral

An auto-calibration circuit minimizes input offset voltage in an integrated circuit analog input device. The auto-calibration circuit may also calibrate a plurality of analog input devices on an integrated circuit die or in a multi-chip package (MCP). The auto-calibration circuit and analog input device(s) may be fabricated in combination with a microcontroller system on an integrated circuit die or in an MCP. The auto-calibration circuit controls input offset voltage compensation circuit that counteracts or compensates for input offset voltage so as to minimize voltage error at the output of the analog input device. A digital control circuit applies a digital word to the input offset voltage compensation circuit for generating the required input offset voltage compensation. A linear search or binary search of various values of the digital word may be used by the digital control circuit. The digital control circuit switches the inputs, the output and feedback-gain determining resistors for the analog input device during a calibration mode. A voltage comparator compares the output of the analog input device and a voltage reference. When the output of the analog input device is equal to or greater than the voltage reference, the comparator output signals the digital control circuit by changing its output logic level. The input offset voltage compensation circuit of the analog input device has a storage register or memory that retains the digital word which compensates for the input offset voltage.

Auto-calibration circuit to minimize input offset voltage in an integrated circuit analog input device

A bandgap voltage comparator requiring the summing of only two current sources is used to detect low voltage conditions for an logic on an integrated circuit that may be powered from a battery, fuel cell, solar cell and the like. Independent high and low voltage trip points may be programmed in the bandgap low voltage detection system. A power-on-reset delay may be used before asserting a voltage level ok status signal. Power may be disconnected from the bandgap voltage comparator low voltage detection system to conserve power, and power can be reapplied to quickly determine whether a desired voltage level is present.

Bandgap voltage comparator used as a low voltage detection circuit

Method of using a bandgap voltage comparator in a low voltage detection circuit

A wake-up reset circuit is provided that generates a reset signal to a digital circuit upon a wake-up event. The wake-up reset circuit places the digital circuit into a known reset condition upon wake-up, even if a brown out condition occurs which may have caused unstable and unknown logic states in sequential circuit elements, e.g., volatile memory, flip flops and/or latching circuits. The wake-up reset circuit draws substantially no current when not generating the reset signal.

Layton Eagar

Papers

Configurable operational amplifier as a microcontroller peripheral

Auto-calibration circuit to minimize input offset voltage in an integrated circuit analog input device

Bandgap voltage comparator used as a low voltage detection circuit

Method of using a bandgap voltage comparator in a low voltage detection circuit

Wake-up reset circuit draws no current when a control signal indicates sleep mode for a digital device