In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

Data processing device and method

Data processing method and device

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Methods and devices for treating and processing data

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

To achieve high performance at low cost, an integrated digital signal processor uses an architecture which includes both a general purpose processor and a vector processor. The integrated digital signal processor also includes a cache subsystem, a first bus and a second bus. The cache subsystem provides caching and data routing for the processors and buses. Multiple simultaneous communication paths can be used in the cache subsystem for the processors and buses. Furthermore, simultaneous reads and writes are supported to a cache memory in the cache subsystem.

Multiprocessor operation in a multimedia signal processor

The integrated digital signal processor has a general purpose processor (210) and a vector processor (220) for operating in parallel with the general-purpose processor. The general-purpose processor has a set of scalar registers, an instruction decoding unit and an instruction processor (200). The vector processor has a set of vector registers and a second instruction decoder and processor. A cache memory (20) is coupled to the general-purpose processor and to the vector processor. The cache memory has simultaneous read and write ports, and holds a data queue coupled to both processors.

Integrated digital signal processor for parallel asymmetric processing of video and audio multi-media

La presente invention concerne un dispositif processeur integre de signaux numeriques. Le dispositif est caracterise en ce qu'il comprend un processeur a tout usage (210) et un processeur de vecteurs (220) pouvant fonctionner en parallele avec le processeur a tout usage (210). Ce dispositif trouve application dans le domaine du multimedia.

Le Trong Nguyen

Papers

Multiprocessor operation in a multimedia signal processor

Integrated digital signal processor for parallel asymmetric processing of video and audio multi-media

Dispositif processeur integre de signaux numeriques