Forest fire is becoming one of the most significant natural disasters at the expense of ecology and economy. In this article, we develop an effective SqueezeNet based asymmetric encoder-decoder U-shape architecture, Attention U-Net and SqueezeNet (ATT Squeeze U-Net), mainly functions as an extractor and a discriminator of forest fire. This model takes attention mechanism to highlight useful features and suppress irrelevant contents by embedding Attention Gate (AG) units in the skip connection of U-shape structure. In this way, salient features are emphasized so that the proposed method could be competent at forest fire segmentation tasks with a small number of parameters. Specifically, we first replace classical convolution layer by a depthwise one and engage a Channel Shuffle operation as a feature communicator in the Fire module of classical SqueezeNet. Then, this modified SqueezeNet is employed as a substitution of the encoder of Attention U-Net and a corresponding DeFire module designed is combined into the decoder as well. Finally, to classify true fire, we take use of a fragment of the encoder in ATT Squeeze U-Net. The experimental results of modified SqueezeNet integrated Attention U-Net show that a competitive accuracy at 0.93 and an average prediction time at 0.89 second per image are achieved for reliable real-time forest fire detection.

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ATT Squeeze U-Net: A Lightweight Network for Forest Fire Detection and Recognition

Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimization for efficient accelerator design of CNN remains a challenging task. A key component of the accelerator design is a processing element (PE) that implements the convolution operation. To reduce the amount of hardware resources and power consumption, this article provides a new processing element design as an alternate solution for hardware implementation. Modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulky MAC units and typical adder tree respectively. The proposed CNN accelerator design is tested on Zynq-706 FPGA board which achieves a throughput of 87.03 GOP/s for Tiny-YOLO-v2 architecture. The proposed design allows to reduce hardware costs by 24.5% achieving a power efficiency of 61.64 GOP/s/W that outperforms the previous designs.

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Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

The U-Net architecture is a state-of-the-art neural network for semantic image segmentation that is widely used in biomedical research. It is based on an encoder-decoder framework and its vanilla version shows already high performance in terms of segmentation quality. Due to its large parameter space, however, it has high computational costs on both, CPUs and GPUs. In a research setting, inference time is relevant, but not crucial for the results. However, especially in mobile, clinical applications a light and fast variant would allow deep-learning assisted, objective diagnosis at the point of care. In this work, we suggest an optimized, tiny-weight U-Net for an inexpensive hardware accelerator. We first mined the U-Net architecture to reduce computational complexity to increase runtime performance by simultaneously keeping the accuracy on a high level. Using an open, biomedical dataset for high-speed videoendoscopy (BAGLS), we show that we can dramatically reduce the parameter space and computations by over 99.8% while keeping the segmentation performance at 95% of our baseline. Using a custom upscaling routine, we further successfully deployed our optimized U-Net to an EdgeTPU hardware accelerator to gain cost-effective speed improvements on conventional computers and to showcase the applicability of EdgeTPUs for biomedical imaging processing of large images on portable devices. Combining the optimized architecture and the EdgeTPU, we gain a speedup of >79-times compared to our initial baseline while keeping high accuracy. This combination allows to provide immediate results to the clinician, especially in constrained computational environments, and an objective diagnosis at the point of care.

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Efficient Biomedical Image Segmentation on EdgeTPUs at Point of Care

In this work, we present a hardware-efficient architecture for pedestrian detection with neuromorphic Dynamic Vision Sensors (DVSs), asynchronous camera sensors that report discrete changes in light intensity. These imaging sensors have many advantages compared to traditional frame-based cameras, such as increased dynamic range, lower bandwidth requirements, and higher sampling frequency with lower power consumption. Our architecture is composed of two main components: an event filtering stage to denoise the input image stream followed by a low-complexity neural network. For the first stage, we use a novel point-process filter (PPF) with an adaptive temporal windowing scheme that enhances classification accuracy. The second stage implements a hardware-efficient Binary Neural Network (BNN) for classification. To demonstrate the reduction in complexity achieved by our architecture, we showcase a Field-Programmable Gate Array (FPGA) implementation of the entire system which obtains a 86& reduction in latency compared to current neural network floating-point architectures.

On-Device Event Filtering with Binary Neural Networks for Pedestrian Detection Using Neuromorphic Vision Sensors

As a typical artificial intelligence algorithm, the convolutional neural network (CNN) is widely used in the Internet of Things (IoT) system. In order to improve the computing ability of an IoT CPU, this paper designs a reconfigurable CNN-accelerated coprocessor based on the RISC-V instruction set. The interconnection structure of the acceleration chain designed by the predecessors is optimized, and the accelerator is connected to the RISC-V CPU core in the form of a coprocessor. The corresponding instruction of the coprocessor is designed and the instruction compiling environment is established. Through the inline assembly in the C language, the coprocessor instructions are called, coprocessor acceleration library functions are established, and common algorithms in the IoT system are implemented on the coprocessor. Finally, resource consumption evaluation and performance analysis of the coprocessor are completed on a Xilinx FPGA. The evaluation results show that the reconfigurable CNN-accelerated coprocessor only consumes 8534 LUTS, accounting for 47.6% of the total SoC system. The number of instruction cycles required to implement functions such as convolution and pooling based on the designed coprocessor instructions is better than using the standard instruction set, and the acceleration ratio of convolution is 6.27 times that of the standard instruction set.

A Reconfigurable Convolutional Neural Network-Accelerated Coprocessor Based on RISC-V Instruction Set

The Convolutional Neural Network (CNN) has been used in many fields and has achieved remarkable results, such as image classification, face detection, and speech recognition. Compared to GPU (graphics processing unit) and ASIC, a FPGA (field programmable gate array)-based CNN accelerator has great advantages due to its low power consumption and reconfigurable property. However, FPGA’s extremely limited resources and CNN’s huge amount of parameters and computational complexity pose great challenges to the design. Based on the ZYNQ heterogeneous platform and the coordination of resource and bandwidth issues with the roofline model, the CNN accelerator we designed can accelerate both standard convolution and depthwise separable convolution with a high hardware resource rate. The accelerator can handle network layers of different scales through parameter configuration and maximizes bandwidth and achieves full pipelined by using a data stream interface and ping-pong on-chip cache. The experimental results show that the accelerator designed in this paper can achieve 17.11GOPS for 32bit floating point when it can also accelerate depthwise separable convolution, which has obvious advantages compared with other designs.

An FPGA-Based CNN Accelerator Integrating Depthwise Separable Convolution

Convolution neural networks (CNN), support vector machine (SVM) and hybrid CNN-SVM algorithms are widely applied in many fields, including image processing and fault diagnosis. Although many dedicated FPGA accelerators have been proposed for specific networks, such as CNN or SVM, few of them have focused on CNN-SVM. Furthermore, the existing accelerators do not support CNN-SVM, which limits their application scenarios. In this work, we propose a hybrid CNN-SVM accelerator on FPGA. This accelerator utilizes a novel hardware-reuse architecture and unique computation mapping strategy to implement different calculation modes in CNN-SVM so that it can realize resource-efficient acceleration of the hybrid algorithm. In addition, we propose a universal deployment methodology to automatically select accelerator design parameters according to the target platform and algorithm. The experimental results on ZYNQ-7020 show that our implementation can efficiently map CNN-SVM onto FPGA, and the performance is competitive with other state-of-the-art works.

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Hybrid CNN-SVM Inference Accelerator on FPGA Using HLS

The rising popularity of mobile devices, which have high performance in object detection calls for a method to implement our algorithms efficiently on mobile devices. As we know, Deep Learning is a good approach to achieve state-of-the-art results. But it needs lots of computation and resources, mobile devices are often resource-limited because of their small size. Recently, FPGA is a device famous for parallelism and many people try to implement the Deep Learning Networks on FPGA. After our investigation, we choose MobileNet-SSD to implement on FPGA because that this network is designed for mobile devices and its size and cost are relatively smaller. There are also some challenges about implementing the network on FPGA, such as the large demand of resources and low latency, which are pretty important for mobile devices. In this paper, we show a quantization scheme for object detection networks based on FPGA and a process to simulate the FPGA on PC to help us predict the performance of networks on FPGA. Besides, we propose an integer-only inference based on FPGA, which truly reduce the cost of resources greatly. The method of Dynamic Fixed Point is adopted and we make some improvement based on object detection networks to quantize the MobileNet-SSD, which is a suitable object detection network for embedded system. Our improvements make its performance better than Ristretto.

A FPGA-Oriented Quantization Scheme for MobileNet-SSD

With the development of Internet of Things (IoT) and edge computing technology, gas sensor arrays based on Micro-Electro-Mechanical System (MEMS) fabrication technique have broad application prospects in intelligent integrated systems, portable devices, and other fields. In such complex scenarios, the normal operation of a gas sensing system depends heavily on the accuracy of the sensor output. Therefore, a lightweight Self-Detection and Self-Calibration strategy for MEMS gas sensor arrays is proposed in this paper to monitor the working status of sensor arrays and correct the abnormal data in real time. Evaluations on real-world datasets indicate that the strategy has high performance of fault detection, isolation, and data recovery. Furthermore, our method has low computation complexity and low storage resource occupation. The board-level verification on CC1350 shows that the average calculation time and running power consumption of the algorithm are 0.28 ms and 9.884 mW. The proposed strategy can be deployed on most resource-limited IoT devices to improve the reliability of gas sensing systems.

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Lei Feng

Papers

An FPGA-Based CNN Accelerator Integrating Depthwise Separable Convolution

Hybrid CNN-SVM Inference Accelerator on FPGA Using HLS

A FPGA-Oriented Quantization Scheme for MobileNet-SSD

Lightweight Self-Detection and Self-Calibration Strategy for MEMS Gas Sensor Arrays

Correcting biased value estimation in mixing value-based multi-agent reinforcement learning by multiple choice learning