Showing papers by "Lei Wang published in 2008"

Cooperative OFDM for energy-efficient wireless sensor networks

Abstract: This paper presents a new energy-efficient cooperative sensor network scheme. Cooperative nodes shift the carrier frequency of the source node, and the destination node receives the signal from the source node and the cooperative nodes as a standard orthogonal frequency division multiplexing (OFDM) receiver. The maximal ratio combining (MRC) approach is applied to achieve full diversity with low complexity. The proposed scheme is scalable with respect to the number of nodes and is robust to time synchronization. A clustered network topology and cooperation protocol are proposed to realize multi-hop long haul signal transmission. The effect of the cluster scale is studied thoroughly to obtain the optimal size of clusters subject to the cooperation overhead. Simulation results show that the proposed cooperation scheme can consistently reduce the transmission power with the increase of cooperation scale. However, there is an optimal cluster scale where a good tradeoff between the diversity gain and cooperation cost can be established to minimize the total power consumption of the whole network.

Programmable threshold voltage using quantum dot transistors for low-power mobile computing

Abstract: Advances in semiconductor technology has fueled the proliferation of a diversity of hand-held mobile computing devices. However, power consumption has become one of the fundamental barriers for deploying research systems in realistic situations. In particular, leakage power is projected to increase exponentially in future process nodes. This requires power-performance optimization at all levels of design hierarchy. In this paper, we propose to exploit the programmable threshold voltage using quantum dot (QD) transistors for addressing the challenge of energy efficiency in mobile computing systems. The unique programmability of QD transistors enhances design optimization for power-performance trade-off. Simulation results demonstrate significant leakage reduction over conventional techniques.

A Defect-Tolerant Memory Nanoarchitecture Exploiting Hybrid Redundancy

Abstract: Nanoelectronic devices have emerged as the potential fabrics for future computing systems as well as memories. However, due to the imperfect fabrication process, the excessively high defect rates prevent nano memories from being practically feasible. In this paper, we propose a defect-tolerant memory nanoarchitecture for nanowire crossbar memories. By using soft redundancy (runtime utilization of spatial/temporal access locality) in combination with hardware redundancy (redundant columns and rows), the proposed technique can achieve effective defect tolerance while reduce the cost as compared to the existing defect mapping techniques and ECC-based designs. Simulation results on memory systems running SPEC CPU2000 benchmarks demonstrate the effectiveness in defect tolerance and cost efficiency of the proposed approach.

A Quantitative Approach for Analysis of Defect Tolerance in QCA

Abstract: Quantum dot cellular automata (QCA) is one of the emerging nanotechnologies for the design of next generation nanocomputing systems. However, excessive defects at the device level are expected to become a fundamental obstacle for achieving reliable computation in QCA-based integrated systems. In this paper, we present an information-theoretic approach to investigate the relationship between defect tolerance and the redundancy inherent in QCA systems. The proposed method allows us to evaluate the effectiveness of redundancy-based defect tolerance in a quantitative manner.

Design of error-tolerant cache memory for multithreaded computing

Abstract: With the trend towards nanometer billion-transistor integration, reliable computing becomes increasingly challenged by semiconductor process variations and low-level physical effects. This is particularly a problem for on-chip memory circuits. In this paper, we propose an error-tolerant memory design technique based on a unique phenomenon referred to as the inter-thread transient redundancy in multithreaded computing. A new memory microarchitecture is developed that exploits dynamic mapping strategies for compensation of unpredictable performance variations and soft errors. Trace driven simulations on the SPEC CPU2000 benchmarks show the advantages of the proposed technique for improving error tolerance in multithreaded microprocessors.

Making register file resistant to power analysis attacks

Abstract: Power analysis attacks are a type of side-channel attacks that exploits the power consumption of computing devices to retrieve secret information. They are very effective in breaking many cryptographic algorithms, especially those running in low-end processors in embedded systems, sensor nodes, and smart cards. Although many countermeasures to power analysis attacks have been proposed, most of them are software based and designed for a specific algorithm. Many of them are also found vulnerable to more advanced attacks. Looking for a low-cost, algorithm-independent solution that can be implemented in many processors and makes all cryptographic algorithms secure against power analysis attacks, we start with register file, where the operands and results of most instructions are stored. In this paper, we propose RFRF, a register file that stores data with a redundant flipped copy. With the redundant copy and a new precharge phase in write operations, RFRF provides data-independent power consumption on read and write for cryptographic algorithms. Although RFRF has large energy overhead, it is only enabled in the security mode. We validate our method with simulations. The results show that the power consumption of RFRF is independent of the values read out from or written to registers. Thus RFRF can help mitigate power analysis attacks.

Digital Filtering With Unreliable Molecular Electronics

Abstract: Molecular electronics such as silicon nanowires (NWs) and carbon nanotubes (CNTs) have emerged as the potential fabrics for building future nanocomputing systems. However, the non-ideal fabrication process and the consequent excessive defect rates make reliable molecular computing a challenging task. Existing solutions addressing this problem aim at achieving the absolute correctness, which becomes increasingly infeasible due to the prohibitive cost involved. It is noticed that in the context of signal processing applications, absolute correctness is generally unnecessary. This could relax the design constraints on defect tolerance in molecular-scale integration. In this paper, we propose a new approach based on defect-insensitive signal processing. By allowing molecular-scale DSP architectures to bear defects, the proposed framework achieves reliable signal processing while ensures the effectiveness of defect tolerance.

A DSP nanosystem with defect tolerance

Abstract: This paper proposes a new way of employing nanowire (NW) crossbars for digital signal processing (DSP) applications. By employing distributed arithmetic, complicated signal processing tasks can be converted into regular memory operations; thus this architecture is well-suited for NW crossbar technology. A defect-tolerant technique exploiting algorithmic error compensation is proposed to achieve reliable signal processing in the presence of excessive defects. Simulation results show that the DSP nanosystem only introduces minor performance loss under a large range of defect rates and operation conditions. The proposed technique also features good tradeoffs between defect tolerance and the overhead incurred.

Improving Error Tolerance for Multithreaded Register Files

Abstract: Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.

Defect-tolerant digital filtering with unreliable molecular electronics

Abstract: Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (CNT) are considered to be the future computational substrates due to their ultra-high density and superior energy efficiency. However, excessive defects from bottom-up self-assembly fabrication pose a major technological barrier to achieving reliable computing at the molecular scale. Existing solutions targeting absolute correctness introduce high cost and complexity in post-fabrication testing and defect diagnosis. In this paper, we propose a new approach exploiting algorithm level enhancements for defect-insensitive signal processing. By deliberately allowing molecular-scale integrated systems to bear defects, the proposed design framework achieves reliable signal processing while significantly reduces the cost of defect tolerance.

Design of Digital Signal Processing Modules with Nanoelectronics

Abstract: This paper presents a new approach of employing nanowire (NW) crossbars for digital signal processing (DSP) applications. By employing the distributed arithmetic (DA), complicated signal processing tasks can be converted into regular memory operations. Thus, this architecture matches well with the technological characteristics of NW crossbars. A new defect- tolerant technique exploiting the abundant data redundancy inherent in the DA module is proposed to achieve error-resilient signal processing with defect-prone NW crossbars. The performance of the proposed approach is demonstrated through a finite impulse response (FIR) filter. Simulation results show that the DA-based nano DSP modules can tolerate excessive defects with minor performance degradation under a range of defect rates and operation conditions.

Design of Digital Signal Processing Modules with

Abstract: This paper presents a new approach of employing nanowire (NW) crossbars for digital signal processing (DSP) applications. By employing the distributed arithmetic (DA), complicated signal processing tasks can be converted into regular memory operations. Thus, this architecture matches well with the technological characteristics of NW crossbars. A new defect- tolerant technique exploiting the abundant data redundancy inherent in the DA module is proposed to achieve error-resilient signal processing with defect-prone NW crossbars. The perfor- mance of the proposed approach is demonstrated through a finite impulse response (FIR) filter. Simulation results show that the DA-based nanoDSP modules can tolerate excessive defects with minor performance degradation under a range of defect rates and operation conditions.