Preface. About the Authors. Acknowledgments. 1 Power Amplifier Fundamentals. 1.1 Introduction. 1.2 Definition of Power Amplifier Parameters. 1.3 Distortion Parameters. 1.4 Power Match Condition. 1.5 Class of Operation. 1.6 Overview of Semiconductors for PAs. 1.7 Devices for PA. 1.8 Appendix: Demonstration of Useful Relationships. 1.9 References. 2 Power Amplifier Design. 2.1 Introduction. 2.2 Design Flow. 2.3 Simplified Approaches. 2.4 The Tuned Load Amplifier. 2.5 Sample Design of a Tuned Load PA. 2.6 References. 3 Nonlinear Analysis for Power Amplifiers. 3.1 Introduction. 3.2 Linear vs. Nonlinear Circuits. 3.3 Time Domain Integration. 3.4 Example. 3.5 Solution by Series Expansion. 3.6 The Volterra Series. 3.7 The Fourier Series. 3.8 The Harmonic Balance. 3.9 Envelope Analysis. 3.10 Spectral Balance. 3.11 Large Signal Stability Issue. 3.12 References. 4 Load Pull. 4.1 Introduction. 4.2 Passive Source/Load Pull Measurement Systems. 4.3 Active Source/Load Pull Measurement Systems. 4.4 Measurement Test-sets. 4.5 Advanced Load Pull Measurements. 4.6 Source/Load Pull Characterization. 4.7 Determination of Optimum Load Condition. 4.8 Appendix: Construction of Simplified Load Pull Contours through Linear Simulations. 4.9 References. 5 High Efficiency PA Design Theory. 5.1 Introduction. 5.2 Power Balance in a PA. 5.3 Ideal Approaches. 5.4 High Frequency Harmonic Tuning Approaches. 5.5 High Frequency Third Harmonic Tuned (Class F). 5.6 High Frequency Second Harmonic Tuned. 5.7 High Frequency Second and Third Harmonic Tuned. 5.8 Design by Harmonic Tuning. 5.9 Final Remarks. 5.10 References. 6 Switched Amplifiers. 6.1 Introduction. 6.2 The Ideal Class E Amplifier. 6.3 Class E Behavioural Analysis. 6.4 Low Frequency Class E Amplifier Design. 6.5 Class E Amplifier Design with 50# Duty-cycle. 6.6 Examples of High Frequency Class E Amplifiers. 6.7 Class E vs. Harmonic Tuned. 6.8 Class E Final Remarks. 6.9 Appendix: Demonstration of Useful Relationships. 6.10 References. 7 High Frequency Class F Power Amplifiers. 7.1 Introduction. 7.2 Class F Description Based on Voltage Wave-shaping. 7.3 High Frequency Class F Amplifiers. 7.4 Bias Level Selection. 7.5 Class F Output Matching Network Design. 7.6 Class F Design Examples. 7.7 References. 8 High Frequency Harmonic Tuned Power Amplifiers. 8.1 Introduction. 8.2 Theory of Harmonic Tuned PA Design. 8.3 Input Device Nonlinear Phenomena: Theoretical Analysis. 8.4 Input Device Nonlinear Phenomena: Experimental Results. 8.5 Output Device Nonlinear Phenomena. 8.6 Design of a Second HT Power Amplifier. 8.7 Design of a Second and Third HT Power Amplifier. 8.8 Example of 2nd HT GaN PA. 8.9 Final Remarks. 8.10 References. 9 High Linearity in Efficient Power Amplifiers. 9.1 Introduction. 9.2 Systems Classification. 9.3 Linearity Issue. 9.4 Bias Point Influence on IMD. 9.5 Harmonic Loading Effects on IMD. 9.6 Appendix: Volterra Analysis Example. 9.7 References. 10 Power Combining. 10.1 Introduction. 10.2 Device Scaling Properties. 10.3 Power Budget. 10.4 Power Combiner Classification. 10.5 The T-junction Power Divider. 10.6 Wilkinson Combiner. 10.7 The Quadrature (90 ) Hybrid. 10.8 The 180 Hybrid (Ring Coupler or Rat-race). 10.9 Bus-bar Combiner. 10.10 Other Planar Combiners. 10.11 Corporate Combiners. 10.12 Resonating Planar Combiners. 10.13 Graceful Degradation. 10.14 Matching Properties of Combined PAs. 10.15 Unbalance Issue in Hybrid Combiners. 10.16 Appendix: Basic Properties of Three-port Networks. 10.17 References. 11 The Doherty Power Amplifier. 11.1 Introduction. 11.2 Doherty's Idea. 11.3 The Classical Doherty Configuration. 11.4 The 'AB-C' Doherty Amplifier Analysis. 11.5 Power Splitter Sizing. 11.6 Evaluation of the Gain in a Doherty Amplifier. 11.7 Design Example. 11.8 Advanced Solutions. 11.9 References. Index.

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High Efficiency RF and Microwave Solid State Power Amplifiers

In this paper, a Wilkinson power divider operating at two arbitrary different frequencies is presented. The structure of this power divider and the formulas used to determine the design parameters have been given. Experimental results show that all the features of a conventional Wilkinson power divider, such as an equal power split, impedance matching at all ports, and a good isolation between the two output ports can be fulfilled at two arbitrary given frequencies simultaneously

A dual-frequency wilkinson power divider

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A novel generalized coupled-line circuit structure for a dual-band Wilkinson power divider is proposed. The proposed power divider is composed of two coupled lines with different even- and odd-mode characteristic impedances and two lumped resistors. Using rigorous even- and odd-mode analysis, the analytical design equations for this proposed power divider are obtained and the ideal closed-form scattering parameters are constructed. Since the traditional transmission line is a special case of coupled line (coupled coefficient is zero), it is found that traditional noncoupled-line dual-band (including single band) Wilkinson power dividers and previous dual-band coupled-line power dividers are special cases of this generalized power divider. As a typical example, which could only be designed by using this given design equations, a compact microstrip 3-dB power divider operating at both 1.1 and 2.2 GHz is designed, fabricated, and measured. There is good agreement between calculated and measured results.

An Analytical Approach for a Novel Coupled-Line Dual-Band Wilkinson Power Divider

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

A Wilkinson power divider operating not only at one frequency f/sub 0/, but also at its first harmonic 2f/sub 0/ is presented. This power divider consists of two branches of impedance transformer, each of which consists of two sections of 1/6-wave transmission-line with different characteristic impedance. The two outputs are connected through a resistor, an inductor, and a capacitor. All the features of a conventional Wilkinson power divider, such as an equal power split, impedance matching at all ports, and a good isolation between the two output ports, can be fulfilled at f/sub 0/ and 2f/sub 0/, simultaneously.

A dual-frequency Wilkinson power divider: for a frequency and its first harmonic

An H.F. power amplifier is disclosed having a plurality of branches (10, 11, 12) switched in parallel. Each branch comprises a plurality of amplifier elements (T1,…, T4) switched in series. Resistors (R2,…, R5) enable the voltage (UlDS) applied to the amplifier elements (T1,…, T4) to be set at a fraction of a supply voltage (Ud) applied to the branches (10, 11, 12). Capacitors (C2,…, C4) are used to adjust the source impedance of the amplifier elements (T2,…, T4). In order to prevent the gate-drain voltage (UlGD) from exceeding the breakdown voltage of an amplifier element (T1,…, T4) and damaging the amplifier element (T1,…, T4), a limiting path (7) is connected according to the invention between the gate terminal (G) and the drain terminal (D) of the amplifier element (T1,…, T4), the limiting path (7) being switchable between a conducting state and a blocking state depending on the gate-drain voltage (UlGD).

Power amplifier for amplifying high-frequency (H.F.) signals

In this work, the three in practice mostly used power amplifiers (PAs), namely the single-ended class AB, the balanced and the Doherty power amplifiers have been implemented for the modern RF mobile telecommunications system in base-station application, using the same LDMOS devices Excellent performance have been obtained by all the three concepts Comparing the experimental results, this paper gives an overview of the advantages and disadvantages of each individual power amplifier

Comparison of a single-ended class AB, a balance and a Doherty power amplifier

Using ST 0.13-mum CMOS technology, a class A power amplifier has been developed for the global system for mobile communication in Europe. To solve the problem of low breakdown voltage in deep-submicrometer CMOS technology, the high-voltage/high-power (HiVP) device configuration is used. With the HiVP configuration, a large voltage can be divided by several devices so that the voltage drop on each device can be limited under the breakdown voltage. The measurement results show that the output power of 29.5 dBm has been achieved at the frequency of 900 MHz. The linear power gain reaches 11.5 dB and the maximum power-added efficiency is as high as 34.5%.

Lei Wu

Papers

A dual-frequency wilkinson power divider

A dual-frequency Wilkinson power divider: for a frequency and its first harmonic

Power amplifier for amplifying high-frequency (H.F.) signals

Comparison of a single-ended class AB, a balance and a Doherty power amplifier

A 900-MHz 29.5-dBm 0.13-μm CMOS HiVP Power Amplifier