Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).

Methods and apparatuses for operating a data processing system

For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

Operating point management in multi-core architectures

In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor Other embodiments are described and claimed

Providing per core voltage and frequency control

A battery system monitoring device includes a plurality of battery monitoring circuits, which is respectively provided in cell groups, and a balancing resistor. Each of the battery monitoring circuits includes a cell voltage measurement unit to measure a cell voltage of each single battery cell at predetermined timing, a discharge switch to switch a state of a discharge current which flows from each single battery cell through the balancing resistor, and a balancing control unit configured to control the discharge switch. A filter circuit is connected between the cell voltage measurement unit and each single battery cell. The cell voltage measurement unit determines whether a cell voltage is measured within a transient response period corresponding to a time constant of the filter circuit and corrects a measurement value of a cell voltage by using a correction value correcting a result of the determination.

Battery system monitoring device

A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.

System and method for controlling central processing unit power with guaranteed transient deadlines

Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.

Power management for multiple processor cores

The operating rate of an electronic system is maximized without exceeding a thermal constraint, such as a maximum junction temperature of an integrated circuit (IC) or other portion of the electronic system. An operating parameter of the system that controls the thermal output of the system is calculated for an upcoming time period based upon the previously measured thermal performance relationship to the operating parameter level. If the predicted thermal performance will exceed a maximum allowable level of the thermal constraint, then the operating parameter is reduced by an amount calculated to keep the thermal constraint at a level just below the maximum allowable level, thus resulting in an optimal control approach to maximizing the system performance while not exceeding the thermal constraint.

Combining power prediction and optimal control approaches for performance optimization in thermally limited designs

A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode.

Method for optimizing voltage-frequency setup in multi-core processor systems

Methods and apparatus relating to deterministic management of dynamic thermal response of processors are described. In one embodiment, available thermal headroom may be used to extract the performance potential in a deterministic way, e.g., such that it reduces or even eliminates the product-to-product variations. Other embodiments are also disclosed and claimed.

Deterministic management of dynamic thermal response of processors

Briefly, a method to control a temperature of a processor and a processor that includes a thermal controller to control a temperature. The thermal controller may decrease the power level of the processor to a first power level for a first predetermined time period and may vary the power of the processor to a second power level for a second predetermined time period.

Lev Finkelstein

Papers

Power management for multiple processor cores

Combining power prediction and optimal control approaches for performance optimization in thermally limited designs

Method for optimizing voltage-frequency setup in multi-core processor systems

Deterministic management of dynamic thermal response of processors

Method and apparatus to control temperature of processor