An automated test equipment (ATE) apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The tester processor is operable to generate commands and data from instructions received from the system controller for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes. The FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes.

Automated test equipment (ATE) support framework for solid state device (SSD) odd sector sizes and protection modes

Fast parallel CRC determination to support SSD testing includes a test data pattern generator for generating test data for storage onto a memory storage device under test (DUT), wherein the generator is operable to generate, every clock cycle, a respective N bit word comprising a plurality of M bit subwords, a digest circuit operable to employ a digest function on each N bit word to produce, every clock cycle, a respective word digest for each N bit word, and a storage circuit operable to store each N bit word along with an associated word digest to the DUT. The digest circuit includes a plurality of first circuits each operable to perform a first digest function on a respective subword of the plurality of subwords, in parallel, to produce a plurality of subword digests, a plurality of second circuits each operable to perform a second digest function on a respective subword digest of the plurality of subword digests, the second digest function being equivalent to shifting the respective subword digest through a linear feedback shift register (LFSR) then followed by (I×M) zero bits, wherein I is related to a word position, within the N bit word, of a respective subword that generated the respective subword digest, and an XOR circuit operable to XOR outputs of the plurality of second circuits together along with a shifted prior LFSR state to produce the word digest of the N bit word.

Fast parallel CRC determination to support SSD testing

Automated test equipment (ate) apparatus, method for testing using ate, and tester

The invention discloses a FPGA reconstruction device and method; the FPGA reconstruction device comprises a host machine, a main control unit FPGA, a tested FPGA, and a SD card; the host machine, the tested FPGA, and the SD card are respectively connected with the main control unit FPGA; the host uses the main control unit FPGA to write tested FPGA needing configuration files into the SD card; the host also uses the main control unit FPGA to write a control program into the tested FPGA; the tested FPGA sends a control signal to the main control unit FPGA according to the control program, thus obtaining configuration files one by one; the FPGA reconstruction method uses the FPGA reconstruction device; the FPGA reconstruction device and method can solve the problems that repetition work amount is big in a FPGA testing process, thus reducing device re-power starting times in a circuit.

Li Shengjie

Papers

FPGA reconstruction device and method