The pinned photodiode is the primary photodetector structure used in most CCD and CMOS image sensors. This paper reviews the development, physics, and technology of the pinned photodiode.

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A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

The charge transfer efficiency improvement method is introduced by optimizing the electrical potential distribution under the transfer gate along the charge transfer path. A non-uniform doped transfer transistor channel is introduced to provide an ascending electrical potential gradient in the transfer transistor channel. With the adjustments to the overlap length between the R1 region and the transfer gate, the doping dose of the R1 region, and the overlap length between the anti-punch-through (APT) implantations and transfer gate, the potential barrier and potential pocket in the connecting region of transfer transistor channel and the pinned photodiode (PPD) are reduced to improve the electrical potential connection. The simulation results show that the percentage of residual charges to total charges drops from 1/104 to 1/107, and the transfer time is reduced from 500 to 110 ns. This means the charge transfer efficiency is improved.

https://iopscience.iop.org/article/10.1088/1674-4926/33/12/124004/pdf

Charge transfer efficiency improvement of a 4-T pixel by the optimization of electrical potential distribution under the transfer gate

A dynamic range extension scheme applied to a time delay integration (TDI) CMOS image sensor (CIS) is presented. Two types of pixels with higher and lower conversion gain are adopted in the pixel array, which are suitable for capturing images in low and high illumination respectively. By fusing the two kinds of pixels' output signals in the process of TDI accumulation, a high dynamic range image can be achieved. Compared with the traditional multiple integration technique, no photoelectrons generated during the exposure time are discarded by the reset operation, and thus a higher level of signal-to-noise ratio (SNR) can be retained. A prototype chip with an 8 × 8 pixel array is implemented in a 0.18 μm CIS process, and the pixel size is 15 × 15 μm2. Test results show that a 76 dB dynamic range can be achieved in 8-stage TDI mode, when the SNR boost can reach 7.26 dB at 90.8 lux.

http://iopscience.iop.org/article/10.1088/1674-4926/35/2/024013/pdf

A dynamic range extension scheme applied to a TDI CMOS image sensor

Pixel devices and arrays of pixel devices are operable to demodulate modulated light incident on a photo-detection region of the pixel devices. The pixel devices can include floating diffusion implant layers and transfer gates. The floating diffusion implant layers and transfer gates are disposed such that photo-generated charge carriers can be conducted to the floating diffusion implant layers over minimal charge-carrier transport paths.

Demodulation pixel devices, arrays of pixel devices and optoelectronic devices incorporating the same

A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size Based on the emission current theory, a qualitative photoresponse model is established to the preliminary prediction Further analysis of noise for incomplete charge transfer predicts the noise variation The test pixels were fabricated in a specialized 018 μm CMOS image sensor process and two different processes of buried N layer implantation are compared The trend prediction corresponds with the test results, especially as it can distinguish an unobvious incomplete charge transfer The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size

http://iopscience.iop.org/article/10.1088/1674-4926/34/5/054009/pdf

Analysis of incomplete charge transfer effects in a CMOS image sensor

In order to increase collection efficiency and eliminate image lag, multi n-type implants were introduced into the process of a pinned-photodiode For the purpose of improving the collection efficiency, multi n-type implants with different implant energies were proposed, which expanded the vertical collection region To reduce the image lag, a horizontal gradient doping concentration eliminating the potential barrier was also formed by multi n-type implants The simulation result shows that the collection efficiency can be improved by about 10% in the long wavelength range and the density of the residual charge is reduced from 259 × 109 to 262 × 107cm−3

https://iopscience.iop.org/article/10.1088/1674-4926/32/12/124008/pdf

Li Weiping

Papers

Collection efficiency and charge transfer optimization for a 4-T pixel with multi n-type implants