An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage

Three dimensional integrated circuits employing thin film transistors

A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.

Programmable logic device

An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.

A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

Semiconductor device having fin-type field effect transistor and method of manufacturing the same

A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

N-channel and p-channel end-to-end finfet cell architecture with relaxed gate pitch

One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

Buffered finfet device

Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits

Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

Programmable logic device memory elements with elevated power supply levels

Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates . When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements .

Volatile memory elements with boosted output voltages for programmable logic device integrated circuits

Integrated circuits such as programmable logic device integrated circuits have arrays of memory elements into which configuration data is loaded. The memory elements are formed form a pair of independently-powered cross-coupled inverters. Control circuitry generates a first inverter power supply signal and a second inverter power supply signal. The first and second inverter power supply signals are distributed to the inverters in the memory elements using pairs of inverter power distribution paths. When it is desired to reset the memory elements, the control circuitry takes the second power supply signal high before the first power supply signal. When it is desired to preset the memory elements, the control circuitry takes the second power supply high after the first power supply signal.

Lin-Shih Liu

Papers

Buffered finfet device

Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits

Programmable logic device memory elements with elevated power supply levels

Volatile memory elements with boosted output voltages for programmable logic device integrated circuits

Preset and reset circuitry for programmable logic device memory elements