Methods for depositing nanolaminate protective layers over a core layer to enable deposition of high quality conformal films over the core layer for use in advanced multiple patterning schemes are provided. In certain embodiments, the methods involve depositing a thin silicon oxide or titanium oxide film using plasma-based atomic layer deposition techniques with a low high frequency radio frequency (HFRF) plasma power, followed by depositing a conformal titanium oxide film or spacer with a high HFRF plasma power.

Soft landing nanolaminates for advanced patterning

The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Contact resistance reduction by new barrier stack process

The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact. The carrier layer preferably comprises a layer formed by ionizing the flux of sputter deposition maternal partially reacting the flux with a gas, and depositing the resulting material on a substrate.

Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches

The present disclosure pertains to our discovery that depositing various film layers in a particular order using a combination of Ion Metal Plasma (IMP) and traditional sputter deposition techniques with specific process conditions results in a barrier layer structure which provides excellent barrier properties and allows for metal/conductor filling of contact sizes down to 0.25 micron and smaller without junction spiking. Specifically, the film layers are deposited on a substrate in the following order: (a) a first layer of a barrier metal (M), deposited by IMP sputter deposition; (b) a second layer of an oxygen-stuffed barrier metal (MOx), an oxygen-stuffed nitride of a barrier metal (MNOx), or a combination thereof; (c) a third layer of a nitride of a barrier metal (MN x ), deposited by IMP sputter deposition of the barrier metal in the presence of nitrogen; and (d) a fourth, wetting layer of a barrier metal, deposited by traditional sputter deposition. The first layer of barrier metal can optionally be annealed to form a silicide of the barrier metal (MSi 2 ) in order to reduce contact resistance and interdiffusion of the silicon and metal/conductor which may result form overetching of contacts. An additional layer of barrier metal can optionally be deposited between the second oxygen-stuffed layer and the third barrier metal nitride layer in order to further improve the barrier properties of the barrier layer structure and to provide for better metal/conductor fill. A thin layer of metal/conductor may be deposited on the walls of the contact via by “long throw” sputter deposition prior to filling the via with metal/conductor in order to provide more uniform fill. The optimum process conditions for sputter deposition of the barrier layer structure of the invention are disclosed herein.

Sputter deposited barrier layers

The present disclosure pertains to our discovery that depositing various film layers in a particular order using a combination of Ion Metal Plasma (IMP) and traditional sputter deposition techniques results in a barrier layer structure which provides excellent barrier properties and allows for metal/conductor filling of contact sizes down to 0.25 micron and smaller without junction spiking. Specifically, the film layers are deposited on a substrate in the following order: (a) a first layer (16) of a barrier metal (M), deposited by IMP sputter deposition; (b) a second layer (20) of an oxygen-stuffed barrier metal (MOx), or an oxygen-stuffed nitride of a barrier metal (MNOx), (c) a third layer (24) of a nitride of a barrier metal (MNx), deposited by IMP sputter deposition; and (d) a fourth, wetting layer (26) of a barrier metal, deposited by traditional sputter deposition. The first layer of barrier metal can optionally be annealed to form a silicide of the barrier metal (MSi2). An additional layer of barrier metal (22) can optionally be deposited between the second oxygen-stuffed layer and the third barrier metal nitride layer.

Oxygen enhancement of ion metal plasma (imp) sputter deposited barrier layers

Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA. Alternative embodiments are also disclosed in which the silicide is formed first, prior to the formation of additional titanium oxynitride by air exposure and RTA, or by sputter deposition. Each of these processes produces a high-quality barrier contact structure overlying a silicide film, where the barrier structure includes titanium oxynitride and titanium nitride.

Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries

Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the, atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA. Alternative embodiments are also disclosed in which the silicide is formed first, prior to the formation of additional titanium oxynitride by air exposure and RTA, or by sputter deposition. Each of these processes produces a high-quality barrier contact structure overlying a silicide film, where the barrier structure includes titanium oxynitride and titanium nitride.

Lin Yih-Shung

Papers

Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries

Integrated circuit with improved contact barrier

Method of fabricating an integrated circuit with improved contact barrier

Integrierte Schaltung mit verbesserter Kontaktbarriere