A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Physical design system and method

Acquired mask data of a defect portion is sent to a simulated repair circuit 300 to be simulated. The simulation of the acquired mask data 204 is returned to the mask inspection results 205 and thereafter sent to a wafer transfer simulator 400 along with a reference image at the corresponding portion. A wafer transfer image estimated by the wafer transfer simulator 400 is sent to a comparing circuit 301. When it is determined that there is a defect in the comparing circuit 301, the coordinates and the wafer transfer image which is a basis for the defect determination are stored as transfer image inspection results 206. The mask inspection results 205 and the transfer image inspection result 206 are then sent to the review device 500.

Defect estimation device and method and inspection system and method

A method and system is disclosed for examining mask pattern fidelity. A mask picture is generated from a first mask with a first OPC model applied to a mask design. The mask picture is converted into a mask based simulation file. A first simulation is conducted under a first set of predetermined lithography processing conditions using the converted simulation file to generate one or more files of a first set representing wafer photo resist profile thereof. The first OPC model is applied to the mask design in the database mask file. A second simulation is conducted under the first set of predetermined lithography processing conditions using the OPCed mask design to generate one or more files of a second set representing wafer photo resist profile thereof. The first and second sets of files are evaluated for inspecting mask fidelity.

System and method for examining mask pattern fidelity

A technique for determining photo-mask defect disposition is described. In this technique, a target mask pattern is used to expand an initial region in a photo-mask that is included in an initial mask-inspection image. In particular, a revised mask-inspection image that includes the initial region and a region surrounding the initial region is generated based on the initial mask-inspection image and the target mask pattern. Then a corresponding simulated mask pattern is calculated in an inverse optical calculation using the revised mask-inspection image and an optical model of the mask-inspection system. This simulated mask pattern is used to simulate a wafer pattern in a photo-lithographic process, and disposition of a possible defect in the initial region is subsequently determined based on the simulated wafer pattern and a target wafer pattern.

Extending the field of view of a mask-inspection image

A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether δ1<e1, wherein δ1 represents model vs. exposure difference and e1 represents predetermined criteria. The technique further includes completing the model when δ1<e1.

Scanner based optical proximity correction system and method of use

To exam mask defect impact during the transfer of a mask pattern to a wafer layer, tools can use mask images obtained during mask inspection. Specifically, these tools can also use optical models of such mask images to simulate wafer images. However, when feature sizes become very small, optical models may not provide sufficiently accurate simulation results. Using a photoresist model would yield significantly more accurate simulation results than using an optical model. Unfortunately, resist modeling is very slow, thereby making it commercially impractical. A simulation tool can generate a simulated wafer image having the accuracy of a photoresist model with the speed of an optical model by using a threshold look-up table. In one embodiment, the threshold look-up table could include variables such as feature size, pitch size, feature type, and defect type.

Linyong Pang

Papers

Method and apparatus of wafer print simulation using hybrid model with mask optical images