A system for recognizing the content of a communication in a symbolic language and composed of plural glyphs arranged in a predetermined order, each glyph being the smallest (lowest) informational unit of the language. The system includes a device for inputting a stream of data indicative of the plural glyphs, such as formed in a page of text. That stream is input into a storage means. The stored data is horizontally segmented into discrete lines of text and is then vertically segmented into individual glyphs. Each individual glyph is assigned a unique identifier, whereby all substantially identical glyphs are represented by the same identifier. The identifiers are arranged in a sequence corresponding to the sequence in which the glyphs appeared in the communication, thus representing glyph "words". The system then applies decryption routines which include general cryptographic techniques to the identifiers, their sequences and their interrelationships to determine the equivalent symbol of language corresponding to each identifier. Once the symbol of language corresponding to each identifier has been determined, the machine code equivalent (i.e., code capable of being "understood" and utilized by an electronic computer) is substituted for each identifier, so as to provide a machine readable code representation of the communication, e.g., page of text.

Cryptographic analysis system

An embedded processor system having a single-chip embedded microprocessor with analog and digital electrical interfaces to external systems. A novel processor core uses pipelined execution of multiple independent and dependent concurrent threads, together with supervisory control for monitoring and controlling the processor thread state and access to other components. The pipeline enables simultaneous execution of multiple threads by selectively avoiding memory or peripheral access conflicts through the types of pipeline stages chosen and the use of dual and tri-port memory techniques. The single processor core executes one or multiple instruction streams on one or multiple data streams in various combinations under the control of single or multiple threads.

Multithread embedded processor with input/output capability

When a result obtained upon character recognition of an input image is to be used as text data for a search operation, a proper search operation can be performed even if a character different from the actual character image is stored as text data due to a character extraction error in character recognition processing. An information processing apparatus includes an image scanner for inputting image information, OCR software for recognizing the input image, a text information storage section for storing a recognition result, and document search software for assuming addition of an extra character in a designated search word, forming a pattern obtained by deleting a character from the search word, and searching a document using this pattern.

Information processing method and apparatus, and storage medium storing program for practicing this method

In a data processing system configured to transfer data in words and an apparatus is provided for manipulating, in response to a single manipulation instruction, the contiguous variable length sequence of data stored in bytes including an instruction decoder for decoding a single manipulation instruction, a memory for storing data in words where each but word includes a plurality of bytes, a circuit responsive to the command signal from the instruction decoder to access a contiguous sequence of the bytes from the memory wherein the first byte of the sequence is not stored on a word boundary, and providing the byte sequence to a plurality of data processing registers wherein the first byte of the sequence is aligned with the first registered boundary. Additionally the apparatus includes the capability to provide the contiguous sequence to memory wherein the first byte of the sequence is not stored on a word boundary. The data sequence maybe specified by the number of bytes in the sequence or by a sequence terminating character.

Apparatus for processing character string moves in a data processing system

A variable vectored architecture digital computer provides real-time cont computations for a rocket control system by executing efficient variable-length instructions optimized for such an application by means of a microprogrammed processor and variable length fields within each instruction concept. A parallel architecture with two streams of commands is used with a new command structure. A new, more powerful instruction set was implemented to increase the throughput. Included in these new instructions are a series of block type moves which allow large amounts of data to be moved by loops within the microprogram instead of loops of firmware instructions which are fetched over and over again for each memory address. The new mechanization allows the firmware instruction fields to vary in length from 1 to 16 bits instead of the fixed 4 bit or 12 bit bytes found in the prior art.

Variable architecture computer with vector parallel processor and using instructions with variable length fields

A central processor for use in a data processing system that is adapted for processing sequences of characters. Information identifying a string of characters to be examined, including the memory location for the first character in the sequence and the total number of characters in the sequence, is placed in working registers of the central processor. Other working registers in the central processor receive information corresponding to a predetermined characteristic, which may be a specific character or information identifying another character string. One of several character string instructions then can be processed. In response to a typical character string instructuion, the central processor retrieves each character from the memory and compares it with the predetermined characteristic. Processing continues until either the predetermined characteristic is detected or all the characters in the character string are examined. During processing, the central processor controls an arithmetic-logic condition code during each comparison. When the processing terminates, the condition code indicates whether the character string contained the predetermined characteristic.

Lloyd I. Dickman

Papers

Central processor with instructions for processing sequences of characters