The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change. Updated to cover the mobile computing revolutionEmphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")Includes three review appendices in the printed text. Additional reference appendices are available online.Includes updated Case Studies and completely new exercises.

Computer Architecture, Fifth Edition: A Quantitative Approach

This report presents a methodology for measuring the performance of supercomputers. It includes 13 Fortran programs that total over 50,000 lines of source code. They represent applications in several areas of engi neering and scientific computing, and in many cases the codes are currently being used by computational re search and development groups. We also present the PERFECT Fortran standard, a set of guidelines that allow portability to several types of machines. Furthermore, we present some performance measures and a method ology for recording and sharing results among diverse users on different machines. The results presented in this paper should not be used to compare machines, except in a preliminary sense. Rather, they are presented to show how the methodology has been applied, and to encourage others to join us in this effort. The results should be regarded as the first step toward our objec tive, which is to develop a publicly accessible data base of performance information of this type.

The Perfect Club Benchmarks: Effective Performance Evaluation of Supercomputers

In the past three years, the Perfect BenchmarkTM Suite has evolved from a supercomputer performance evaluation plan, presented by Kuck and Sameh at the 1987 International Conference on Supercomputing, to a vigorous international activity. This paper surveys the current state of this supercomputer performance evaluation effort with particular focus on the adopted methodology. While there has been considerable success in achieving the goals of the plan, some issues remain unresolved, and new questions have surfaced.

Supercomputer performance evaluation and the Perfect Benchmarks

Prefetching methods for instruction caches in supercomputers are studied via trace-driven simulation. The two primary methods studied are fall-through prefetch for sequential line accesses and target prefetch for nonsequential ones. As measured by miss rate, both methods are shown to improve performance significantly. When combined in a hybrid algorithm their performance improvement is cumulative. A prefetch efficiency measure that reflects the amount of memory fetch delay that is successfully hidden by prefetching is defined. The better prefetch methods (in terms of miss rate) also have very high efficiencies, hiding approximately 90% of the miss delay for prefetched lines. The results obtained also show that the top-performing prefetch caches produce less memory traffic than the top-performing nonprefetch caches. >

Prefetching in supercomputer instruction caches

A discussion is presented of the use of dynamic storage schemes to improve parallel memory performance during three important classes of data accesses: vector accesses in which multiple strides are used to access a single vector, block accesses, and constant-geometry FFT accesses. The schemes investigated are based on linear address transformations, also known as XOR schemes. It has been shown that this class of schemes can be implemented more efficiently in hardware and has more flexibility than schemes based on row rotations or other techniques. Several analytical results are shown. These include: quantitative analysis of buffering effects in pipelined memory systems; design rules for storage schemes that provide conflict-free access using multiple strides, blocks, and FFT access patterns; and an analysis of the effects of memory bank cycle time on storage scheme capabilities. >

Block, multistride vector, and FFT accesses in parallel memory systems

The authors report on their opportunity to benchmark the VP-200 (benchmarked at the Fujitsu plant in Numazu, Japan in May 1984 and more recently in May 1985 at Amdahl); the Hitachi S810/20 (made available at the Large Scale Computation Center of Tokyo University in May 1984); and Cray Research provided time on an X-MP running COS and version 1.13 of their CFT compiler. Other X-MP benchmarks were conducted at Los Alamos. For the most part, the codes that were executed on the machines came from the Los Alamos benchmark set. The set is composed of programs that typify the Los Alamos workload. It was found that the VP-200 can be two to three times as fast as the X-MP/2 in vector mode for large vector lengths. Results from highly vectorized codes (rudimentary matrix operations and a linear equations solver) as well as the timings from basic vector operations support this conclusion. On the codes that are more indicative of the Los Alamos workload, the VP-200 and X-MP/2 are comparable. The times for BMK5 (0% vectorized) were virtually equivalent; BMK21 (0% vectorized) was executed on the VP-200 18% faster than on the X-MP; BMK1lb (62% vectorized) and BMK21a (18% vectorized) favored the VP-200 by 17% and 24%, respectively; and SIMPLE (93% vectorized) favored the X-MP by 25%. The authors suggest three reasons for the parity: (1) from the standpoint of Amdahl's Law, many of the codes are dominated by the equivalent scalar performance of the machines, (2) even in the cases of higher degrees of vectorization, vector lengths less than 100 perform equivalently, and (3) function calls prevented full vectorization on the VP-200 in some cases (for example, BMK1la). The Hitachi S810/20 does not perform as well as the other two on the benchmark codes, probably because its scalar performance and vector processor clock period are slower. Additionally, the benchmark codes could not make use of the large number of functional units in the S810/20.

Lubeck

Papers

A Benchmark Comparison of Three Supercomputers: Fujitsu VP-200, Hitachi S810/120, and Cray X-MP/2