A ATM communication system can satisfy various requests from a node system, a link system, and the like, by performing a self-format transform between a format to be transmitted and a format receiving an ATM switch, and using a cell processing function for performing polishing/shaping, counting of passed cells, counting of discarded cells, drop/insertion of OAM cell, and the like.

ATM communication system

The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

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Architectural choices in large scale ATM switches

This invention relates to a switch module for use in an asynchronous transfer mode (ATM) system incorporating a shared buffer memory where incoming data cells are stored and subsequently transferred to exit ports. An incoming data cell is stored at a vacant buffer memory address on an interleaved, word-by-word basis and the address is placed in an appropriate priority queue in the appropriate exit port for the data cell. When time is available for transmission from the exit port, the data cell corresponding to the address at the head of the highest priority queue is sent to the exit port and transmitted.

Shared buffer switching module

The authors propose a call admission control scheme based on a method of estimating cell loss quality for individual bursty traffic sources. The estimate is expressed in terms of virtual cell loss probability, which may be defined by two traffic characteristic parameters alone: peak and mean rate. The approach is suitable for the estimation of real cell loss probability in heterogeneous and homogeneous traffic models when burst length is larger than buffer capacity. The concept of virtual cell loss probability is extended to the individual call level so as to be able to estimate the quality of service (QOS) provided to individual calls. A virtual bandwidth method is used to develop a practical call admission control system. Quality is ensured by combining a traffic clustering scheme, with a scheme for assigning individual clusters to subcapacities of a link. Priority levels are presented in terms of the class of QOS required, i.e., deterministic or statistical, and the allocation of virtual bandwidth is discussed in terms of both QOS class and traffic characteristics. >

A call admission control scheme for ATM networks using a simple quality estimate

ATM will provide flexibility in bandwidth allocation and will allow a network to carry heterogeneous services ranging from narrowband to wideband services. The challenge is to build fast packet switches able to match the high speeds of the input links and the high performance requirements imposed. The CCITT has standardized the asynchronous transfer mode (ATM) as the multiplexing and switching principle for the broadband integrated services digital network (B-ISDN). ATM is a packet and connection-oriented transfer mode based on statistical time division multiplexing techniques. The information flow is organized in fixed-size packets called cells, consisting of a user information field (48 octets) and a header (5 octets). The primary use of the header tag is to identify cells belonging to the same virtual channel and to make routing possible. Cell sequence on a virtual channel is preserved, a very low cell loss probability must be guaranteed ( >

ATM shared-memory switching architectures

Being the communication core of future broadband products, the ATM based switching network architecture must comply with a challenging set of future safe requirements and objectives, which are tentatively defined first. After some period of research work, a number of different solutions for fast packet switching or ATM switching are still proposed. It is thus interesting to discuss the respective attributes of key architecture options for asynchronous switch fabrics. As an illustration, the paper then describes a new ATM based switching architecture for asynchronous communications based on the advantageous combination of a multiple-path self-routing principle with an internal transfer mode using multi-slot cells. These principles are the foundation for a flexible and fault tolerant switching network configuration built with two Weis of standard switching components: the Switch Module board equivalent to a 128 x 128 single-stage matrix operating at 150 Mbit/s, and the Integrated Switching Element LSI circuit realizing an elementary, fully featured, 32 x 32 switching matrix.

M.A. Henrion

Papers

Switching network architecture for atm based broadband communications