Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

A new FIFO design that enables fully synchronous circuits with unrelated clocks to communicate synchronously is proposed. Not only would every circuit be running on its own clock, but the interconnection network is fully synchronous and runs at an unrelated clock of its own. With relatively low gate count, the proposed FIFO allows communicating circuits to put/get data at their respective frequencies (1 datum/clock cycle) till it gets filled then the rates converge to the lower frequency. The maximum initial latency is 3 cycles of the consumer's clock. Several manifestations of the proposed FIFO have been developed for different design cases including data width mismatch between producer and consumer. The operation of different FIFOs has been verified using gate-level simulations for several ratios of clock frequencies. An 8-cell FIFO has been designed at the transistor-level and Spice simulations using a 0.13 μm, 1.2V technology has been carried out. It shows proper operation at producer and consumer clock frequencies of 2GHz and 3.125GHz, respectively, with a data transfer rate of more than 2Giga datum/second and an average power of 721 μW.

A new FIFO design enabling fully-synchronous on-chip data communication network

Recemment le domaine du traitement de l'image, de la video, et l'audio a connu plusieurs evolutions importantes au niveau des algorithmes et des architectures. L'une de ces evolutions est l'apparition du nouveau standard ISO/IEC de compression d'image JPEG2000 qui succede a JPEG. Ce nouveau standard presente de nombreuses fonctionnalites et caracteristiques qui lui permettent d'etre adapte a une large panoplie d'applications. Mais ces caracteristiques se sont accompagnees d'une complexite algorithmique beaucoup plus elevee que JPEG et qui le rend tres difficile a optimiser pour certaines implementations ayant des contraintes tres severes en terme de surface, de temps d'execution ou de consommation d'energie ou de l'ensemble de ces contraintes. L'une des etapes cle dans le processus de compression JPEG2000 est le codeur entropique qui constitue a lui seul environ 70% du temps de traitement global pour la compression d'une image. Il est donc essentiel d'analyser les possibilites d'optimisation d'implementations de JPEG2000. Les circuits FPGA sont aujourd'hui les principaux circuits reconfigurables disponibles sur le marche. S'ils ont longtemps ete utilises uniquement pour le prototypage des ASIC, ils sont aujourd'hui en mesure de fournir une solution efficace a la realisation materielle d'applications dans de nombreux domaines. Vu le progres que connait l'industrie des composants FPGA du point de vue capacite d'integration et frequence de fonctionnement, les architectures reconfigurables constituent aujourd'hui une solution efficace et competitive pour repondre aussi bien aux besoins du prototypage qu'a ceux des implementations materielles. Dans ce travail nous proposons une demarche pour l'etude des possibilites d'implementations de JPEG2000. Cette etude a debute avec l'evaluation d'implementations logicielles sur plateformes commerciales. Des optimisations logicielles ont ete ajoutees en utilisant des librairies SIMD specialisees exploitant du parallelisme a grain fin. Suite a cette premiere etude on a realise une implementation materielle d'un bi codeur entropique sur FPGA qui a servi comme coprocesseur pour deux plateformes distinctes l'une etant une machine hote et l'autre un systeme industriel embarque. Suite a cette etape nous avons fait evoluer l'implementation en passant a une deuxieme approche qui est l'approche systeme sur puce programmable. Dans cette derniere partie nous avons effectue le partitionnement materiel/logiciel du codeur entropique sur FPGA, puis une implementation multi codeur a ete realisee sur FPGA et utilisee comme coprocesseur sur puce pour la creation d'un systeme sur puce programmable. Ces differents travaux ont permis de couvrir une partie de l'espace des applications que JPEG2000 peut cibler. En meme temps ces implementations donnent une vue globale sur les possibilites des implementations de JPEG2000 ainsi que leurs limites. De plus cette etude represente un moyen pour decider de l'adequation architecture application de JPEG2000.

https://pastel.archives-ouvertes.fr/pastel-00001658/document

Optimisation de JPEG 2000 sur système sur puce programmable

In this work we present four digital synthesis tools capable of converting finite state machines modeled in Petri nets into a corresponding VHDL description. Mealy or Moore finite state machine models are represented in Place/Transition Petri nets through two possible methodologies, developed during this work. With one of the methodologies only Mealy machines can be modeled, while the with other both Mealy and Moore type machines can be dealt with. The methodologies and the kind of Petri net translation one desires to obtain are essential factors to determine the tools to be used. Two among the tools we developed translate a Petri net description into a state transition table, while the other two translate the Petri net description into a VHDL behavioral one. Depending on which of them is used it is also necessary to use some other synthesis tools developed by members of our research group. The adequacy of the developed methodologies an tools to the synthesis process has been verified through the simulation of the VHDL codes generated by our tools.

https://www.feis.unesp.br/Home/departamentos/engenhariaeletrica/pos-graduacao/186-dissertacao_giorgety_licorini_dias.pdf

Ferramentas para a integração de redes de Petri e VHDL na síntese de sistemas digitais

Wishbone is a standard System-on-Chip (SoC) bus interface for Intellectual Property (IP) core modules to communicate with each other. The present day SoCs have large number of interconnected cores/processing-elements (PE) that need to communicate with each other. Typical scenario would have a Master processor/Controller-Core and large number of Slave/hardware-accelerator/co-processor/PE cores. These cores may have their own local private memory and may share memory blocks with other cores. The cores need to transfer data/instructions between themselves, peripherals and input-output ports. In case of applications demanding Single-Kernel-Multiple-Data (SKMD), the Controller core may transfer the common kernel-code to PEs using Broadcast or Multicast technique rather than transmitting the same kernel-code multiple times. Similarly the controller core can transfer the common data to multiple cores using Broadcast or Multicast technique in the case of Multiple-Kernel-Single-Data (MKSD). In this paper, it is exhibited that Wishbone protocol capability can be enhanced by including Multicasting and Broadcasting features. Promising results have been achieved with simulation and synthesis of the whole module on Xilinx 14.4 ISE platform. Design has been implemented on Xilinx FPGA platform using Nexys-4 (Artix-7) board.

Enhancement of Wishbone protocol with broadcasting and multicasting

An interface process generation methodology, based on Petri nets, is described for fast integrating point-to-point communicating modules. Formal basis of this methodology ease behavioral property-checking and consistent execution of the generated interface process. The exposed technique allows fast incorporation of third-party cores into SoPC systems design where integration task is often a barrier for reusability.

Petri net based interface analysis for fast IP-core integration

The system on a chip (SoC) has become a reality, hosting the design of complex circuits into a single programmable device, supporting different cores for microprocessors, interfaces, buses, etc. However, the automatic inclusion of new general cores, from different providers, via a standard bus still needs a reliable interface mechanism to guarantee the correct protocol conversion and performance. This work presents a CAD tool to cope with this problem, based on a Petri net protocol conversion approach in a high level behavioral specification, focusing on bus planning and core integration.

M.E. de Lima

Papers

Petri net based interface analysis for fast IP-core integration

A fast IP-core integration methodology for SoC design