RuleBase is a formal verification tool, developed by the IBM Haifa Research Laboratory. It is the result of three years of experience in practical formal verification of hardware which, we believe, has been a key factor in bringing the tool to its current level of maturity. We present the tool, including several unique features, and summarize our usage experience.

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RuleBase: an industry-oriented formal verification tool

The specification language RCTL, an extension of CTL, is defined by adding the power of regular expressions to CTL. In addition to being a more expressive and natural hardware specification language than CTL, a large family of RCTL formulas can be verified on-the-fly (during symbolic reachability analysis). On-the-fly model checking, as a powerful verification paradigm, is especially efficient when the specification is false and extremely efficient when the computation needed to get to a failing state is short. It is suitable for the inherently gradual design process since it detects a multitude of bugs at the early verification stages, and paves the way towards finding the more complex errors as the design matures. It is shown that for every erroneous finite computation, there is an RCTL formula that detects it and can be verified on-the-fly. On-the-fly verification of RCTL formulas has moved model checking in IBM into a different class of designs inaccessible by prior techniques.

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On-the-Fly Model Checking of RCTL Formulas

On-the-fly model checking of RCTL formulas

We propose algorithms which combine simulation with symbolic methods for the verification of invariants. The motivation is two-fold. First, there are designs which are too complex to be formally verified using symbolic methods; however the use of symbolic techniques in conjunction with traditional simulation results in better “coverage” relative to the computational resources used. Additionally, even on designs which can be symbolically verified, the use of a hybrid methodology often detects the presence of bugs faster than either formal verification or simulation.

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On Combining Formal and Informal Verification

We introduce SImulation Verification with Augmentation (SIVA), a tool for checking safety properties on digital hardware designs. SIVB integrates simulation with symbolic techniques for vector generation. Specifically, the core algorithm uses a combination of ATPG and BDDs to generate input vectors which cover behavior not excited by simulation. Experimental results demonstrate considerable improvement in state space coverage compared with either simulation or formal verification in isolation.

Enhancing simulation with BDDs and ATPG

We show how we have successfully identified the bug of a real chip by using formal verification techniques. Since excessive number of simulation cycles are necessary to debug the chip design, formal verification techniques, specifically CTL symbolic model checking, were adopted to identify the bug. We demonstrate several approaches including abstraction, which make it possible to apply symbolic model checking methods. The methods and ideas reported here are general enough for diagnosing other real chips. >

M. Fujita

Papers

Bug identification of a real chip design by symbolic model checking