This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Introduction to flash memory

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current. >

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Reliability issues of flash memory cells

A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.

Flash EEPROM array with negative gate voltage erase operation

A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel architecture of this invention includes means for erasing through the gate of the flash EEPROM cell.

Flash EEPROM array with paged erase architecture

This paper describes an electrically programmable and erasable nonvolatile memory cell employing a single floating gate transistor (1), and its implementation in a 512K CMOS EEPROM memory chip. The single transistor EEPROM cell is based on an innovative device concept, and utilizes proven process techniques. The cell is programmed to a high Vt state by channel hot electron injection like an EPROM cell, and erased to a low Vt state by Fowler Nordheim tunneling from the floating gate to source diffusion. With the proper choice of gate dielectric and cell layout the cell is programmed to high threshold with less than 5 volts on the drain and less than 15 volts on the control gate. Erasing is achieved with less than 15 volts on the source diffusion. A 25 square micron cell has been implemented in a 512K EEPROM memory chip with a die size of 4.3 mm. by 7 mm.

M. Knecht

Papers

A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM