Alvin R. Lebeckt Matrix multiplication is an important kernel in linear algebra algorithms, and the performance of both serial and parallel implementations is highly dependent on the memory system behavior. Unfortunately, due to false sharing and cache conflicts, traditional column-major or row-major array layouts incur high variability in memory system performance as matrix size varies. This paper investigates the use of recursive array layouts for improving the performance of parallel recursive matrix multiplication algorithms. We extend previous work by Frens and Wise on recursive matrix multiplication to examine several recursive array layouts and three recursive algorithms: standard matrix multiplication, and the more complex algorithms of Strassen and Winograd. We show that while recursive array layouts significantly outperform traditional layouts (reducing execution times by a factor of 1.2-2.5) for the standard algorithm, they offer little improvement for Strassen’s and Winograd’s algorithms; we provide an algorithmic explanation of this phenomenon. We demonstrate that carrying the recursive layout down to the level of individual matrix elements is counterproductive, and that a combination of recursive layouts down to canonically ordered matrix tiles instead yields higher performance. We evaluate five recursive layouts with successively increasing complexity of address computation, and show that addressing overheads can be kept in control even for the most computationally demanding of these layouts. Finally, we provide a critique of the Cilk system that we used to parallelize our code.

Recursive array layouts and fast parallel matrix multiplication

Addition forms the basis of digital computer systems. Three novel gate level full adder designs, based on the elements of a standard cell library are presented in this work: one design involving XNOR and multiplexer gates (XNM), another design utilizing XNOR, AND, Inverter, multiplexer and complex gates (XNAIMC) and the third design incorporating XOR, AND and complex gates (XAC). Comparisons have been performed with many other existing gate level full adder realizations. Based on extensive simulations with a 32-bit carry-ripple adder implementation; targeting three process, voltage and temperature (PVT) corners of the high speed (low Vt) 65nm STMicroelectronics CMOS process, it was found that the XAC based full adder is found to be delay efficient compared to all its gate level counterparts, even in comparison with the full adder cell available in the library. The XNM based full adder is found to be area efficient, while the XNAIMC based full adder offers a slight compromise with respect to speed and area over the other two proposed adders.

/pdf/high-speed-gate-level-synchronous-full-adder-designs-1wihlejg2b.pdf

High speed gate level synchronous full adder designs

In this paper, we investigate the problem of designing embedded decentralized discrete-event controllers over communication networks. It is assumed that there is a path between every pair of processes in the network. The control objective is specified by a prefix-closed language that is controllable and observable, but not coobservable. The paper is focused on communication among processes necessary to meet the control objective. As such, process models are left unspecified; it is only required that disabling any of the controllable events do not block communication among processes. Our findings support the idea that in the presence of ideal communication channels, the protocol design for noncoobservable specifications can be reduced to the synthesis of communicating decentralized supervisors, and we propose solutions for a restricted class of problems. The paper is concluded with a positive result for the case where channels are unreliable.

/pdf/decentralized-supervisory-control-of-discrete-event-systems-512loabeor.pdf

Decentralized Supervisory Control of Discrete-Event Systems Over Communication Networks

It is widely recognized that programs with Graphical User Interfaces (GUIs) are difficult to design and implement. One possible reason for this difficulty is the lack of any clear formal basis for GUI programming. GUI toolkit libraries are typically described only informally, in terms of implementation artifacts such as objects, imperative state and I/O systems. 
In this thesis, we develop Fruit, a Functional Reactive User Interface Toolkit. Fruit is based on Yampa, an adaptation of Functional Reactive Programming (FRP) to the Arrows computational framework. Yampa has a clear, simple formal semantics based on a synchronous dataflow model of computation. GUIs in Fruit are defined compositionally using only the Yampa model and formally tractable mouse, keyboard and picture types. Fruit and Yampa have been implemented as libraries for Haskell, a purely functional programming language. 
This thesis presents the semantics and implementations of Yampa and Fruit, and shows how they can be used to write concise executable specifications of common GUI programming idioms and complete GUI programs.

https://antonycourtney.com/pubs/ac-thesis.pdf

Modeling user interfaces in a functional language

http://repository.kulib.kyoto-u.ac.jp/dspace/bitstream/2433/179144/1/j.physleta.2013.07.042.pdf

Counter operation in nonlinear micro-electro-mechanical resonators

From the Publisher:
This is a modern revision of the classic digital design textbook. The book teaches the basic tools for the design of digital circuits in a clear, easily accessible manner. 

New to This Edition: 

Nine sections on Verilog Hardware Description Language (HDL) inserted in discrete sections, allowing the material to be covered or skipped as desired. The Verilog HDL presentation is at a suitable level for beginning students who are learning digital circuits for the first time. 
Reorganized material on combinational circuits is now covered in a single chapter. 
The emphasis in the sequential circuits chapters is now on design with D flip-flops instead of JK and SR flip-flops. 
The material on memory and programmable logic is now consolidated in one chapter. 
Chapter 8 consists mostly of new material and now covers digital design in the Register Transfer Level (RTL), preparing the reader for more advanced design projects and further Verilog HDL studies. 
A new section in Chapter 11 supplements the laboratory experiments with HDL experiments. These enable the reader to check the circuits designed in the laboratory by means of hardware components and/or by HDL simulation. 
Text accompanied by Verilog simulator software>SynaptiCAD's VeriLogger Pro evaluation version, a Verilog simulation environment that combines all of the features of a traditional Verilog simulator with a powerful graphical test vector generator. Fast model testing in VeriLogger Pro allows the reader to perform bottom-up testing of every model in a design. All of the HDL examples in thebook can be found on the CD-ROM. 
A Companion Website includes resources for instructors and students such as transparency masters of all figures in the book, all HDL code examples from the book, a Verilog tutorial, tutorials on using the VeriLogger Pro software, and more. 

CONTENTS

Binary Systems
Boolean Algebra and Logic Gates 
Gate-Level Minimization
Combinational Logic 
Synchronous Sequential Logic 
Registers and Counters 
Memory and Programmable Logic 
Register Transfer Level 
Asynchronous Sequential Logic 
Digital Integrated Circuits 
Laboratory Experiments 
Standard Graphic Symbols

M. Morris Mano

Papers

Digital Design