Sleep State Switching

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Programmable application specific integrated circuit and logic cell therefor

A method and apparatus redundantly store data, in particular video data objects, in a distributed computer system having at least three processor systems, each processor system being connected in point to point two way channel interconnection with each other processor system. The data is stored in a redundant fashion both at the computer system level as well as the processor system level. Accordingly, the failure of a single processor does not adversely affect the integrity of the data. The computer system can also overlay a switching system connected in a ring fashion for providing a fault tolerance to the failure of a single connected processor system at the switch level. Accordingly, there results a fault tolerant data distribution system.

Loosely coupled mass storage computer cluster

A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Semiconductor integrated circuit device having power reduction mechanism

Managing the power consumption of computing platforms is a complicated problem thanks to a multitude of hardware configuration options and characteristics. Much of the academic research is based on unrealistic assumptions, and has, therefore, seen little practical uptake. We provide an overview of the difficulties facing power management schemes when used in real systems.We present Koala, a platform which uses a pre-characterised model at run-time to predict the performance and energy consumption of a piece of software. An arbitrary policy can then be applied in order to dynamically trade performance and energy consumption. We have implemented this system in a recent Linux kernel, and evaluated it by running a variety of benchmarks on a number of different platforms. Under some conditions, we observe energy savings of 26% for a 1% performance loss.

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Koala: a platform for OS-level power management

Featuring a strong emphasis on the fundamentals underlying contemporary logic design using hardware description languages, synthesis, and verification, this book focuses on the ever-evolving applications of basic computer design concepts with strong connections to real-world technology. Treatment of logic design, digital system design, and computer design. Ideal for self-study by engineers and computer scientists.

Logic and Computer Design Fundamentals

PART I. 1. Binary Numbers and Codes. 2. Digital Circuits. 3. Combinational Systems. 4. Sequential Logic. PART II. 5. Registers and Counters. 6. Memory and Programmable Logic. 7. Register Transfer and Computer Operations. 8. Control Logic Design. PART III. 9. Computer Instructions and Addressing Modes. 10. Design of a Central Processing Unit (CPU). 11. Input-Output and Communication. 12. Memory Management. Index.

M. Morris Mano

Papers

Logic and Computer Design Fundamentals

Computer Engineering: Hardware Design

Computer system architecture (3rd ed.)

Digital design (2nd ed.)

Logic and Computer Design Fundamentals and Xilinx Student Edition 4.2 Package (3rd Edition)