This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06-mm2 silicon area in a 0.13-μm CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration

A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves >10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 ?m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

/pdf/a-low-power-capacitive-charge-pump-based-pipelined-adc-33ckjovx61.pdf

A Low-Power Capacitive Charge Pump Based Pipelined ADC

This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40-kS/s A/D converter (ADC) with an active die area of 0.041 mm2 is implemented in a 0.13-mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4-muW power dissipation, the ADC achieves 80.2-dB spurious-free dynamic range and 63.3-dB signal-to-noise and distortion ratio.

A 12-Bit Ratio-Independent Algorithmic A/D Converter for a Capacitive Sensor Interface

A fully differential switched-capacitor (SC) amplifier and integrator with an accurate gain of 2 are proposed. Both circuits are based on a novel capacitor mismatch compensation scheme which uses the same capacitor as the charge sampling and summing element. Therefore, the gain error which is linearly proportional to the capacitor mismatch in conventional SC circuits becomes proportional to the square of the mismatch. In addition, the proposed scheme does not require additional active blocks, and the valid output is generated within two clock cycles.

/pdf/sc-amplifier-and-sc-integrator-with-an-accurate-gain-of-2-1wevs00awi.pdf

SC amplifier and SC integrator with an accurate gain of 2

A conversion operation B is performed with respect to a sample value R in an A/D conversion stage 101 to generate a conversion result D3, and a sampling operation A is performed with respect to this conversion result D3 in an A/D conversion stage 103. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 105 to generate a conversion result D4, and the sampling operation A is performed with respect to the conversion result D4 in an A/D conversion stage 107. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 107 to generate a conversion result D5, and the sampling operation A is performed with respect to this conversion result D5 in an A/D conversion stage 101. The conversion operation B is performed with respect to a sample value in the A/D conversion stage 103 to generate a conversion result D6, and the sampling operation A is performed with respect to the conversion result D6 in the A/D conversion stage 105.

Analog digital converter, a/d conversion stage, method for generating digital signal corresponding to analog signal, and method for generating signal indicating conversion error in the a/d conversion stage

This paper presents a novel circuit architecture for the accurate realization of the basic 1.5-bit ADC stage common to switched capacitor algorithmic and pipelined ADCs. A floating buffer is proposed which enables the accurate addition of signal voltages without requiring precision components. 14-bit ADC linearity is demonstrated with uncharacterized metal-metal capacitors without the need for calibration or trimming. A prototype 12-bit 3.3 MS/s algorithmic ADC in 0.25 /spl mu/m standard CMOS is described. The power FOM is 1.2 pJ/conversion and the area FOM is 31 nm/sup 2//conversion - well below previously reported figures for algorithmic ADCs.

M. Pribytko

Papers

Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 /spl mu/m CMOS