Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.

Nanowire-based programmable architectures

The charge storage characteristics of atomic layer deposited RuOx nanocrystals embedded in high-k HfO2∕Al2O3 films in a metal/Al2O3∕RuOx∕HfO2∕SiO2∕n-Si structure have been investigated. The size and density of RuOx nanocrystals have been measured using transmission electron microscopy. The RuOx nanocrystals show a density of ∼1×1012∕cm2 and a diameter of 5–8nm. A large hysteresis memory window of ∼13.3V at a gate voltage of 9V has been observed for RuOx nanocrystal memory capacitors. A hysteresis memory window of 0.7V has also been observed under a small sweeping gate voltage of 1V. A promising memory window of RuOx nanocrystals has been observed as compared with those of pure HfO2 and Al2O3 charge trapping layers, due to charge storage in the RuOx metal nanocrystals. The RuOx nanocrystal memory capacitor has similar leakage current with the pure HfO2 and Al2O3 charge trapping layers. The RuOx memory capacitor has a large breakdown voltage of ∼13.8V.

Charge storage characteristics of atomic layer deposited RuOx nanocrystals

Nanowire building blocks provide a promising path to small feature size and thus the ability to more densely pack logic. However, the small feature size and novel, bottom-up manufacturing process will exhibit extreme variation and produce many devices that operate outside acceptable operating ranges. One-mapping-fits-all, prefabrication assignment of logical functions to physical transistors that exhibit high threshold variation will not work—combining the wide range of physical variation in transistor threshold voltage with the wide range of fanouts in the design produces an unworkably large composite range of possible delays. Nonetheless, by carefully matching the fanout of each net to the physical threshold voltages of devices after fabrication, it is possible to reduce the net range of path delays sufficiently to achieve high system yield. By adding a modest amount of extra resources, we achieve 100% yield for systems built out of devices with 38% variation, the ITRS prediction for threshold variation in 5nm transistors. Moreover, for these systems, we maintain delay, energy and area close to the variation-free nominal case.

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VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems

Both bottom-up and top-down techniques have been used to fabricate assemblies of devices and interconnect where key, density-defining feature sizes are on the order of ten atoms wide. We show how complete computing architectures can be constructed from these new techniques and building blocks despite high defect rates, extreme regularity requirements, and statistical assembly. We further highlight the paradigm shifts in integrated circuit design and architecture which appear necessary to accommodate these atomic-scale effects. Our estimates suggest a 10 nm full-pitch FPGA-like design can achieve one to two orders of magnitude greater logic density than ideal, defect-free lithographic scaling to 22 nm.

Architecture approaching the atomic scale

Owing to the scaling demands, source/drain (S/D) junction engineering has evolved as a promising technique to improve the performance and reliability of NAND flash memory devices. In this paper, we investigate the impact of S/D doping lateral straggle $\sigma _{L}$ on the program characteristics, data retention, and short-channel effects (SCEs) for sub-25-nm NAND flash memory device. Here, we consider threshold voltage roll-off, subthreshold slope, and drain-induced barrier lowering parameters to study the SCE for the aforementioned memory device. We also examine the effect of varying $\sigma _{L}$ on the junction boost leakage current [during the program-inhibition (P-I) mode] for the considered device. Based on our investigations, we have shown that adjusting the S/D doping lateral straggle $\sigma _{L}$ appropriately not only improves SCE but also the program speed and data retention without any need of altering the gate oxide stack. Furthermore, the junction boost leakage current also decreases on reducing $\sigma _{L}$ . Consequently, it enables the device to hold high channel potential during the P-I mode, and thereby reduces the risk of false programming/erasing of the device.

Improved Short-Channel Characteristics With Long Data Retention Time in Extreme Short-Channel Flash Memory Devices

The use of nanoscale channel MOSFETs as a candidate for future nonvolatile memory is extensively investigated. The device consists of a wire channel MOSFET with nanometer dimensions on which Si nanocrystals (Si-NCs) are deposited. The memory characteristics as a function of the channel widths for different channel lengths are presented. The channel length dimensions are defined between 100-1000 nm by electron beam lithography and the width dimensions are reduced from a few tens of nanometers down to sub-5 nm by wet etching and thermal oxidation processes. It is found that the controllability of the fabrication process is enhanced as the channel length is reduced to 100 nm. Moreover, memory performances are improved with decreasing channel width due to the bottleneck effect. These results show that the Si-NCs memory is highly scalable in terms of the channel size. In the narrowest channel devices, i.e., in the sub-5-nm range, coulomb-blockade oscillations are obtained due to the ultra-small regions formed in the channel. In such devices, a strong enhancement of the retention characteristics has been found as a result of the quantum mechanical narrow channel effect in the ultra-narrow channel.

M. Saitoh

Papers

Channel width and length dependence in Si nanocrystal memories with ultra-nanoscale channel