A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affected by the electrical disturbances. Next, principles of superposition are utilized to coherently combine each of the electrical disturbance waveforms in the time domain to generate the predicted SSO noise waveform that is imposed upon the affected signal conduction path. The electrical disturbance waveforms may be produced either by using bench measurements performed on an actual integrated circuit, by simulation, or by a combination of simulation and bench measurements.

Method for predicting simultaneous switching output (SSO) noise

Design practices and issues in controlling Simultaneous Switching Noise

LSI design method considering power supply noise

This work describes an efficient methodology for the analysis of simultaneous switching noise in an integrated system of a microchip in its package and board environment. This methodology has been used to analyze and identify the noise from I/O cell simultaneous switching output (I/O SSO) on a large network processor design in 130 nm technology. This methodology provides a fast and accurate global I/O SSO analysis that can be applied during the design phase to identify I/O SSO effects and their impact on the core. The supply noise predicted by the I/O SSO analysis was correlated with full-chip results of a true dynamic AC noise analysis flow and verified with measurements on silicon.

M. Schmitt

Papers

Simultaneous switching noise analysis for full-chip power integrity sign-off