Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

A low cost ATE-based cache resident test methodology is presented in this paper for testing cores of microprocessor chips with non-deterministic main memory access. No non-determinism (ND) or training sequence handling of the SerDes is needed, simplifying test development, reducing the need for expensive next generation ATE that handle SerDes, and simplifying debug as the SerDes are not tested or used. Even low cost testers (LCT) with low speed interface support initially developed for structural test can be enabled to run these tests.

Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues

A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a first time, a second time and a third time and determines whether the transition occurs between the first time and the second time and whether it occurs between the first time and third time and generates an increment/decrement signal indicating a position for the transition. A strobe adjust circuit generates a strobe signal based on the increment/decrement signal. A capture circuit captures the received digital data signal using the strobe signal.

Tracker circuit and method for automated test equipment systems

This paper presents a Built-In Self-Test (BIST) scheme to measure high speed double data rate (DDR) memory output timing using low cost testers. This technique uses an on-chip pattern generator to generate a time delay between data and data-strobe or clock. The time delay is controlled precisely using a phase interpolator based cycle-by-cycle control method. A novel method for testing the resolution of phase interpolator, which does not need any extra hardware, is also presented. Using the test resolution, a timing pass/fail flag is set and the timing margin is quantified as a multiple of the test clock cycle. Since these test results have high observability, output per-pin timing performance can be diagnosed easily, which is especially good for testing parallel memory interfaces. Moreover, these features make our scheme compatible with low-cost testers and decreases the time-to-market for the chip. The BIST circuit has been implemented using the 0.18-µm CMOS process, and chip measurement results are presented. We obtained a test resolution of 10 ps for testing output timing. Using the fabricated test chip, this paper shows the effects of switching noise, per-pin skews and slew-rate change on output timing variations.

A Built-In Self-Test scheme for DDR memory output timing test and measurement

This paper proposed the design and implementation of high speed communication link between two FPGAs using LVDS driver using 100 MHz clock. Initially Asynchronous and Synchronous communication are discussed and then synchronous communication is used for LVDS data communication. The speed of the communication is sensitive to the noise and sampling of the data at the receiver end. Therefore, the differential signal voltage level and sampling at the falling edge of clock are proposed in the design to maintain the high speed.

Design of High-Speed LVDS Data Communication Link Using FPGA

A majority of digital logic devices receives stimulus from an external system clock and sends information out on bus pins which are synchronized to the system clock. During functional testing of such devices, ATE architectures supply the clock and input data signals. The output signals generated by these devices are synchronous to the tester and are sampled accurately by the test equipment's strobe circuits. With the emergence of wide data busses in memories and high speed communication protocols implemented to transfer data between the CPU and peripherals, it has become necessary to forward a clock along with a group of bus pins to maintain skew across the high speed bus pins to an acceptable value for system design. This has resulted in a class of devices which have source synchronous busses where output signals are sent out relative to their strobe (output clock) signals. This work describes the challenges associated with testing this class of devices with the classical automatic test equipment (ATE) architecture and presents a unique hardware solution implemented on a contemporary tester architecture to meet the test challenge. This work also compares this implementation with other solutions available in the ATE domain.

M. Shimanouchi

Papers

Tester architecture for the source synchronous bus