A fully-distributed arbiter for multiprocessor systems

An arbitration circuit for a multiple bus system was designed using M number of N-to-1 arbiters and one M-user B-server (M-to-B) arbiter, where M, N and B are the number of memory modules, processors and buses, respectively. A new design of an M-to-B arbiter was presented by S.M. Mahmud and M. Showkat-Ul-Alam (1990), but this arbiter does not work properly when one or more buses become faulty, and does not have the reconfigurable feature. The authors present the design of a reconfigurable M-to-B arbiter. The performance of the arbiter has been evaluated using simulation. The results show that the arbiters work as they are supposed to under different bus fault conditions. >

/pdf/fault-tolerant-arbiters-for-synchronous-multiple-bus-systems-1wusv49kyq.pdf

Fault tolerant arbiters for synchronous multiple bus systems

An arbitration device includes an arbitration section, a counter, and a changing section While write request signals and read request signals for a transfer path, are inputted from request sources, the arbitration section arbitrates an order that the write and read request signals use the transfer path, and when arbitration is settled, outputs use permission signals to the request sources The changing section changes a time from outputting of the write request signals until inputting of the write request signals to the arbitration section, and/or a time from outputting of the use permission signals for the write request signals until inputting of the use permission signals to the request sources

Arbitration device, arbitration method, image processing device, and image forming system

A two-level decentralized bus arbitration network for a hierarchical bus system is developed. To achieve distributed control and ensure fairness among the competing processors, the rotating daisy chain implementation scheme is used in this design. The authors discuss the hierarchical bus system (HBS) architecture, the HBS arbitration algorithm, the generation of bus requests through the processor bus requests (PBR) generation circuitry, and the arbitration of requests of a bus memory arbiter (BMA). The proposed arbiter uses a simpler control mechanism by using distributed control and ensures fairness by dynamically changing the priorities of the devices connected to the bus. With this arbitration scheme, the HBS system is more efficient than a corresponding multiple bus system in terms of the number of transactions that can be carried out. >

Decentralized arbiter design for a synchronous hierarchical bus multiprocessor system

The paper presents the arbiter design using one level and two level lookahead technique with two step arbitration for N-user B-server case with favorite and non-favorite priorities. The implementation of the proposed arbiter can work more efficiently and faster than the iterative method and is fairer and more complete than pure lookahead technique in the realistic multiprocessor system. >

http://ieeexplore.ieee.org/iel2/1096/8013/00342968.pdf

A lookahead arbiter for n-user b-server with non-favorite priority

A novel design for an M-user B-server arbiter for a multiple bus system is presented. The arbitration circuit maintains fairness when it is used in a low-order interleaved memory system. The arbiter is also fair for a general-purpose multiprocessor system where the memory modules are uniformly accessed by the processors. The arbitration time grows at a rate O(log/sub 2/ M), where M is the number of memory modules in a system. When a system has more than four memory modules, both the gate count and delay of the present design are less than those of previous designs. >

http://ece.eng.wayne.edu/~smahmud/PersonalData/PubPapers/IEEE-ISCS-Jun-1991.pdf

M. Showkat-Ul-Alam

Papers

A new arbitration circuit for synchronous multiple bus multiprocessor systems